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Commit Graph
648 Commits
Author SHA1 Message Date
Blaise Tine 124acfbf12 texture unit dcache arbitration 2021-03-18 14:23:53 -04:00
Krishna Yalamarthy 6febdf7399 pt sampling - dcache arb; pt address compute setup 2021-03-17 12:07:25 -04:00
Blaise Tine 2cbc1c4161 adding texture test to tex_demo 2021-03-17 09:52:33 -04:00
Blaise Tine 676a13f30d tex refactoring and bug fixes 2021-03-16 09:25:57 -04:00
Blaise Tine 17424ad554 Merge remote-tracking branch 'origin/master' into graphics 2021-03-15 18:23:28 -04:00
Blaise Tine fb46c65d25 Merge branch 'graphics' of https://github.com/vortexgpgpu/vortex-dev into graphics 2021-03-15 18:02:02 -04:00
Blaise Tine 6a9a279a32 build fixes and cleanup 2021-03-15 17:59:53 -04:00
Blaise Tine a79253329c relaxing commit back-pressure in writeback stage 2021-03-15 14:39:55 -07:00
Krishna YalamarthyandBlaise Tine 72e06ef4fe Tex CSRs write support added 2021-03-15 16:41:29 -04:00
Krishna YalamarthyandBlaise Tine 7587876820 Texture Instruction - Fixed Color 2021-03-15 16:41:28 -04:00
Krishna Yalamarthy a953fe4e1e Tex CSRs write support added 2021-03-13 22:01:25 -05:00
Krishna Yalamarthy f3f62e9e7b Texture Instruction - Fixed Color 2021-03-12 18:33:04 -05:00
Blaise Tine 66ea340d05 Fix RAM memory deallocation 2021-03-09 01:52:56 -08:00
Blaise Tine 10a994d11a csr minor update 2021-03-08 03:46:07 -08:00
Blaise Tine 062d02ddce Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2021-03-04 20:51:03 -08:00
Blaise Tine 8a86bddd3e fixed simX multicore support, added shared memory 2021-03-04 20:45:27 -08:00
Blaise Tine 5e3a949d2d floating-point conversion fix 2021-03-01 06:11:03 -08:00
Blaise Tine b023496ecb minor update 2021-03-01 03:00:58 -08:00
Blaise Tine c8af5a8f45 minor update 2021-03-01 02:56:58 -08:00
Blaise Tine ad06408044 minor update 2021-03-01 01:51:25 -08:00
Blaise Tine 0e3872ee94 floating-point CSR fix 2021-03-01 01:46:41 -08:00
Blaise Tine b441870789 rename use_imm and use_PC 2021-03-01 00:38:46 -08:00
Blaise Tine a9cb0b4ec1 minor update - asesim fix 2021-02-28 17:30:21 -08:00
Blaise Tine e3a11e4a5c minor fix 2021-02-28 14:18:43 -08:00
Blaise Tine 3f5fd6d394 using shiftreg-based skid buffers 2021-02-28 02:20:09 -08:00
Blaise Tine e64996946d using 44-bit perf counters - aligned with DSP counters width 2021-02-28 02:05:47 -08:00
Blaise Tine 8a9a67aa5a minor update 2021-02-27 21:54:55 -08:00
Blaise Tine f5a17bd1a9 decode optimization and refactoring 2021-02-27 18:21:41 -08:00
Blaise Tine ebee332e9d minor update 2021-02-27 02:31:05 -08:00
Blaise Tine 20d704b4d3 skid buffer optimization 2021-02-27 02:29:48 -08:00
Blaise Tine 34ce0b8e89 minor update 2021-02-23 20:54:03 -08:00
Blaise Tine 700f9eea19 moving MUL unit into ALU unit 2021-02-23 13:49:02 -08:00
Blaise Tine 1792571e1b minor update 2021-02-22 13:30:45 -08:00
Blaise Tine 1346d64ba9 minor update 2021-02-22 04:04:13 -08:00
Blaise Tine 7560202f8b cache bank refactoring - removing unecessary core response fifo & restoring single port data access 2021-02-21 21:47:46 -08:00
Blaise Tine ccb74ef286 cache data access with decoupled read/write ports 2021-02-21 15:18:24 -08:00
Blaise Tine 3e961c4e6e minor update 2021-02-21 15:14:46 -08:00
Blaise Tine 6739dc7923 minor update - registering execute units skid buffers 2021-02-21 15:11:08 -08:00
Blaise Tine f27c1fac5f minor update 2021-02-21 03:38:24 -08:00
Blaise Tine 6d7692da37 minor fix. 2021-02-21 03:37:36 -08:00
Blaise Tine 258eb633a6 minor update 2021-02-20 13:16:25 -08:00
Blaise Tine 05f93fac20 minor update 2021-02-20 13:15:15 -08:00
Blaise Tine 143319d557 minor optimization 2021-02-18 16:03:16 -08:00
Blaise Tine 31b3e380dc minor update 2021-02-15 09:23:40 -08:00
Blaise Tine 9eed48435c instruction decode optimization 2021-02-14 00:19:54 -08:00
Blaise Tine 3c37db877a cache specialization for in-order DRAM reponses 2021-02-13 20:23:29 -08:00
Blaise Tine 073964fdf7 minor update 2021-02-12 08:52:06 -08:00
Blaise Tine ab63ac9e5d cache request interfaces update 2021-02-10 20:55:04 -08:00
Blaise Tine 665b97b810 multi-ported cache support for streaming 2021-02-08 16:13:32 -08:00
Blaise Tine fd1726197b cache merge optimization 2021-02-07 07:33:39 -08:00