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adding texture test to tex_demo

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This commit is contained in:
Blaise Tine
2021-03-17 09:52:33 -04:00
parent 676a13f30d
commit 2cbc1c4161
17 changed files with 654 additions and 632 deletions
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4
hw/VX_config.h
View File

@@ -253,7 +253,7 @@
#define CSR_TEX0_FORMAT CSR_TEX_BEGIN + 0x1
#define CSR_TEX0_WIDTH CSR_TEX_BEGIN + 0x2
#define CSR_TEX0_HEIGHT CSR_TEX_BEGIN + 0x3
#define CSR_TEX0_STRIDE CSR_TEX_BEGIN + 0x4
#define CSR_TEX0_PITCH CSR_TEX_BEGIN + 0x4
#define CSR_TEX0_WRAP_U CSR_TEX_BEGIN + 0x5
#define CSR_TEX0_WRAP_V CSR_TEX_BEGIN + 0x6
#define CSR_TEX0_MIN_FILTER CSR_TEX_BEGIN + 0x7
@@ -264,7 +264,7 @@
#define CSR_TEX1_FORMAT CSR_TEX_BEGIN + 0xA
#define CSR_TEX1_WIDTH CSR_TEX_BEGIN + 0xB
#define CSR_TEX1_HEIGHT CSR_TEX_BEGIN + 0xC
#define CSR_TEX1_STRIDE CSR_TEX_BEGIN + 0xD
#define CSR_TEX1_PITCH CSR_TEX_BEGIN + 0xD
#define CSR_TEX1_WRAP_U CSR_TEX_BEGIN + 0xE
#define CSR_TEX1_WRAP_V CSR_TEX_BEGIN + 0xF
#define CSR_TEX1_MIN_FILTER CSR_TEX_BEGIN + 0x10

39
hw/rtl/VX_config.vh
View File

@@ -238,30 +238,33 @@
`define CSR_NC 12'hFC2
////////// Texture Unit CSRs /////////////
`define CSR_TEX_BEGIN 12'hFD0
// Unit 1
`define CSR_TEX0_ADDR `CSR_TEX_BEGIN
`define CSR_TEX0_FORMAT `CSR_TEX_BEGIN + 12'h1
`define CSR_TEX0_WIDTH `CSR_TEX_BEGIN + 12'h2
`define CSR_TEX0_HEIGHT `CSR_TEX_BEGIN + 12'h3
`define CSR_TEX0_STRIDE `CSR_TEX_BEGIN + 12'h4
`define CSR_TEX0_WRAP_U `CSR_TEX_BEGIN + 12'h5
`define CSR_TEX0_WRAP_V `CSR_TEX_BEGIN + 12'h6
`define CSR_TEX0_MIN_FILTER `CSR_TEX_BEGIN + 12'h7
`define CSR_TEX0_MAX_FILTER `CSR_TEX_BEGIN + 12'h8
`define CSR_TEX0_ADDR `CSR_TEX_BEGIN
`define CSR_TEX0_FORMAT `CSR_TEX_BEGIN + 12'h1
`define CSR_TEX0_WIDTH `CSR_TEX_BEGIN + 12'h2
`define CSR_TEX0_HEIGHT `CSR_TEX_BEGIN + 12'h3
`define CSR_TEX0_PITCH `CSR_TEX_BEGIN + 12'h4
`define CSR_TEX0_WRAP_U `CSR_TEX_BEGIN + 12'h5
`define CSR_TEX0_WRAP_V `CSR_TEX_BEGIN + 12'h6
`define CSR_TEX0_MIN_FILTER `CSR_TEX_BEGIN + 12'h7
`define CSR_TEX0_MAX_FILTER `CSR_TEX_BEGIN + 12'h8
// Unit 2
`define CSR_TEX1_ADDR `CSR_TEX_BEGIN + 12'h9
`define CSR_TEX1_FORMAT `CSR_TEX_BEGIN + 12'hA
`define CSR_TEX1_WIDTH `CSR_TEX_BEGIN + 12'hB
`define CSR_TEX1_HEIGHT `CSR_TEX_BEGIN + 12'hC
`define CSR_TEX1_STRIDE `CSR_TEX_BEGIN + 12'hD
`define CSR_TEX1_WRAP_U `CSR_TEX_BEGIN + 12'hE
`define CSR_TEX1_WRAP_V `CSR_TEX_BEGIN + 12'hF
`define CSR_TEX1_MIN_FILTER `CSR_TEX_BEGIN + 12'h10
`define CSR_TEX1_MAX_FILTER `CSR_TEX_BEGIN + 12'h11
`define CSR_TEX1_ADDR `CSR_TEX_BEGIN + 12'h9
`define CSR_TEX1_FORMAT `CSR_TEX_BEGIN + 12'hA
`define CSR_TEX1_WIDTH `CSR_TEX_BEGIN + 12'hB
`define CSR_TEX1_HEIGHT `CSR_TEX_BEGIN + 12'hC
`define CSR_TEX1_PITCH `CSR_TEX_BEGIN + 12'hD
`define CSR_TEX1_WRAP_U `CSR_TEX_BEGIN + 12'hE
`define CSR_TEX1_WRAP_V `CSR_TEX_BEGIN + 12'hF
`define CSR_TEX1_MIN_FILTER `CSR_TEX_BEGIN + 12'h10
`define CSR_TEX1_MAX_FILTER `CSR_TEX_BEGIN + 12'h11
`define CSR_TEX_END `CSR_TEX1_MAX_FILTER
// Pipeline Queues ////////////////////////////////////////////////////////////
// Size of LSU Request Queue

4
hw/rtl/VX_define.vh
View File

@@ -389,9 +389,7 @@
`define MAXHTW 8
`define MAXFTW 8
`define MAXFMW 8
`define MAXAMW 8
`define TAGW 8
`define DATAW 32
`define MAXAMW 8
////////////////////////////////////////////////////////////////////////////////////////
`include "VX_types.vh"

8
hw/rtl/tex_unit/VX_tex_unit.v
View File

@@ -55,7 +55,7 @@ module VX_tex_unit #(
`CSR_TEX0_FORMAT : tex_format[0] <= tex_csr_if.write_data;
`CSR_TEX0_WIDTH : tex_width[0] <= tex_csr_if.write_data;
`CSR_TEX0_HEIGHT : tex_height[0] <= tex_csr_if.write_data;
`CSR_TEX0_STRIDE : tex_stride[0] <= tex_csr_if.write_data;
`CSR_TEX0_PITCH : tex_stride[0] <= tex_csr_if.write_data;
`CSR_TEX0_WRAP_U : tex_wrap_u[0] <= tex_csr_if.write_data;
`CSR_TEX0_WRAP_V : tex_wrap_v[0] <= tex_csr_if.write_data;
`CSR_TEX0_MIN_FILTER : tex_min_filter[0] <= tex_csr_if.write_data;
@@ -65,7 +65,7 @@ module VX_tex_unit #(
`CSR_TEX1_FORMAT : tex_format[1] <= tex_csr_if.write_data;
`CSR_TEX1_WIDTH : tex_width[1] <= tex_csr_if.write_data;
`CSR_TEX1_HEIGHT : tex_height[1] <= tex_csr_if.write_data;
`CSR_TEX1_STRIDE : tex_stride[1] <= tex_csr_if.write_data;
`CSR_TEX1_PITCH : tex_stride[1] <= tex_csr_if.write_data;
`CSR_TEX1_WRAP_U : tex_wrap_u[1] <= tex_csr_if.write_data;
`CSR_TEX1_WRAP_V : tex_wrap_v[1] <= tex_csr_if.write_data;
`CSR_TEX1_MIN_FILTER : tex_min_filter[1] <= tex_csr_if.write_data;
@@ -88,7 +88,7 @@ module VX_tex_unit #(
assign rsp_PC = tex_req_if.PC;
assign rsp_rd = tex_req_if.rd;
assign rsp_wb = tex_req_if.wb;
assign rsp_data = {`NUM_THREADS{32'hFAAF}}; // dummy color value
assign rsp_data = {`NUM_THREADS{32'hFF0000FF}}; // dummy blue value
// output
assign stall_out = ~tex_rsp_if.ready && tex_rsp_if.valid;
@@ -116,7 +116,7 @@ module VX_tex_unit #(
$display("%t: core%0d-tex_csr: csr_tex0_format, csr_data=%0h", $time, CORE_ID, tex_format[0]);
$display("%t: core%0d-tex_csr: csr_tex0_width, csr_data=%0h", $time, CORE_ID, tex_width[0]);
$display("%t: core%0d-tex_csr: csr_tex0_height, csr_data=%0h", $time, CORE_ID, tex_height[0]);
$display("%t: core%0d-tex_csr: csr_tex0_stride, csr_data=%0h", $time, CORE_ID, tex_stride[0]);
$display("%t: core%0d-tex_csr: CSR_TEX0_PITCH, csr_data=%0h", $time, CORE_ID, tex_stride[0]);
$display("%t: core%0d-tex_csr: csr_tex0_wrap_u, csr_data=%0h", $time, CORE_ID, tex_wrap_u[0]);
$display("%t: core%0d-tex_csr: csr_tex0_wrap_v, csr_data=%0h", $time, CORE_ID, tex_wrap_v[0]);
$display("%t: core%0d-tex_csr: csr_tex0_min_filter, csr_data=%0h", $time, CORE_ID, tex_min_filter[0]);