felsabbagh3
|
d8e25045be
|
Added All Interfaces
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2020-03-03 22:48:49 -08:00 |
|
felsabbagh3
|
73cecd3866
|
Added Core Interface
|
2020-03-03 22:14:56 -08:00 |
|
felsabbagh3
|
01ae6ffafe
|
Added Core Interface
|
2020-03-03 22:14:56 -08:00 |
|
felsabbagh3
|
57a96e02b1
|
Fixed some other timing issues
|
2020-03-03 21:15:44 -08:00 |
|
felsabbagh3
|
58db00f555
|
Fixed some other timing issues
|
2020-03-03 21:15:44 -08:00 |
|
felsabbagh3
|
08986bf1dc
|
Fixed incorrect valid and'ing in execute
|
2020-03-03 20:57:20 -08:00 |
|
felsabbagh3
|
25b6dbdfa8
|
Fixed incorrect valid and'ing in execute
|
2020-03-03 20:57:20 -08:00 |
|
felsabbagh3
|
a47f7c11ec
|
Finished cache, dram imp + interfaces left
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2020-03-03 19:42:33 -08:00 |
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felsabbagh3
|
733d00aba9
|
Finished cache, dram imp + interfaces left
|
2020-03-03 19:42:33 -08:00 |
|
felsabbagh3
|
8ece8d8893
|
Fixed miss reserv to support ST->LD sequences
|
2020-03-03 17:04:39 -08:00 |
|
felsabbagh3
|
e2e053ff7b
|
Fixed miss reserv to support ST->LD sequences
|
2020-03-03 17:04:39 -08:00 |
|
felsabbagh3
|
80af320fdb
|
Before fixing miss rsrv for ST->LD sequences
|
2020-03-03 16:57:05 -08:00 |
|
felsabbagh3
|
b150327ca9
|
Before fixing miss rsrv for ST->LD sequences
|
2020-03-03 16:57:05 -08:00 |
|
felsabbagh3
|
361fc2c3fe
|
Finished st0
|
2020-03-03 02:49:30 -08:00 |
|
felsabbagh3
|
8784b09b18
|
Finished st0
|
2020-03-03 02:49:30 -08:00 |
|
felsabbagh3
|
3a970bbe7b
|
Connected cache to bank
|
2020-03-02 23:24:17 -08:00 |
|
felsabbagh3
|
8c6284f627
|
Connected cache to bank
|
2020-03-02 23:24:17 -08:00 |
|
felsabbagh3
|
fc5621cd1d
|
Everything except bank internals
|
2020-03-02 23:08:54 -08:00 |
|
felsabbagh3
|
f6cc05eaa2
|
Everything except bank internals
|
2020-03-02 23:08:54 -08:00 |
|
felsabbagh3
|
abca2f7abb
|
Modified Scheduler to be mask based (allows thread granuility writebacks) + Fixed all LW and SW unit test errors errors
|
2020-03-01 22:27:18 -08:00 |
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felsabbagh3
|
d78338c7d4
|
Modified Scheduler to be mask based (allows thread granuility writebacks) + Fixed all LW and SW unit test errors errors
|
2020-03-01 22:27:18 -08:00 |
|
felsabbagh3
|
6bf25b5b78
|
+Added icache stage -- 3rd case of AUIPC os broken?
|
2020-03-01 18:01:02 -08:00 |
|
felsabbagh3
|
f98f5c414d
|
+Added icache stage -- 3rd case of AUIPC os broken?
|
2020-03-01 18:01:02 -08:00 |
|
wgulian3
|
23aabbf01d
|
Make ALU div/mul pipelines longer and support logic element multiplication mode for better long pipeline performance
|
2020-02-22 20:16:13 -05:00 |
|
wgulian3
|
ca61801199
|
Make ALU div/mul pipelines longer and support logic element multiplication mode for better long pipeline performance
|
2020-02-22 20:16:13 -05:00 |
|
wgulian3
|
b2afe526fe
|
Update multiply for not SYN_FUNC
|
2020-02-21 23:20:04 -05:00 |
|
wgulian3
|
a099cb25cf
|
Update multiply for not SYN_FUNC
|
2020-02-21 23:20:04 -05:00 |
|
wgulian3
|
f2c0453702
|
Add multi-cycle compat module and use it in ALU
|
2020-02-21 22:08:09 -05:00 |
|
wgulian3
|
2c40874cc5
|
Add multi-cycle compat module and use it in ALU
|
2020-02-21 22:08:09 -05:00 |
|
wgulian3
|
83d1f54fcf
|
fix shared mem ram inference
|
2020-02-20 15:59:23 -05:00 |
|
wgulian3
|
e145b8078c
|
fix shared mem ram inference
|
2020-02-20 15:59:23 -05:00 |
|
wgulian3
|
55d722364d
|
Merge branch 'fpga_synthesis' into fix_cache_m10k
|
2020-02-20 02:36:39 -05:00 |
|
wgulian3
|
2d3b790324
|
Merge branch 'fpga_synthesis' into fix_cache_m10k
|
2020-02-20 02:36:39 -05:00 |
|
codetector
|
e82e29c855
|
remove async reset for FPGA synthesis
|
2020-02-19 23:19:05 -05:00 |
|
codetector
|
e901fb6a3a
|
remove async reset for FPGA synthesis
|
2020-02-19 23:19:05 -05:00 |
|
wgulian3
|
de85cfd296
|
fix clean build with makefile
|
2020-02-19 17:33:51 -05:00 |
|
Codetector
|
072c89c433
|
Merge branch 'fpga_synthesis' into fix_cache_m10k
|
2020-02-19 16:03:23 -05:00 |
|
Codetector
|
1a29007bc7
|
Merge branch 'fpga_synthesis' into fix_cache_m10k
|
2020-02-19 16:03:23 -05:00 |
|
wgulian3
|
5dadeffac8
|
fix project.tcl
|
2020-02-19 14:20:58 -05:00 |
|
wgulian3
|
3b60c10460
|
Merge branch 'fpga_synthesis' of github.gatech.edu:casl/Vortex into fpga_synthesis
|
2020-02-19 01:04:55 -05:00 |
|
wgulian3
|
3423e3189f
|
Fix e2e building issues and increase division pipeline length
|
2020-02-19 01:04:48 -05:00 |
|
wgulian3
|
3e68c8bcf5
|
verilator does not support delayed assignment in a loop
|
2020-02-18 13:38:17 -05:00 |
|
wgulian3
|
e76d05f7ce
|
Fix issues quartus synthesis issues
|
2020-02-18 13:24:18 -05:00 |
|
wgulian3
|
d71f8fcc73
|
Fix divide edge case in verilator and move divide modules out of SYN_FUNC block within alu.
|
2020-02-18 13:02:46 -05:00 |
|
wgulian3
|
a32d654263
|
Merge branch 'master' into fpga_synthesis
|
2020-02-18 03:35:12 -05:00 |
|
wgulian3
|
61803741f8
|
Merge branch 'master' into fpga_synthesis
# Conflicts:
# rtl/VX_back_end.v
# rtl/VX_gpr_stage.v
# rtl/VX_writeback.v
# rtl/simulate/test_bench.cpp
# rtl/simulate/test_bench.h
# runtime/mains/dev/Makefile
|
2020-02-18 03:34:38 -05:00 |
|
felsabbagh3
|
28ce40eebf
|
fixed make w + vx_gpr_stage csr schedule
|
2020-02-18 00:26:44 -08:00 |
|
felsabbagh3
|
be66e51613
|
Added CSRs, some Load unit tests are failing
|
2020-02-17 22:22:27 -08:00 |
|
felsabbagh3
|
a0f3f67426
|
Fixed double printing in ::io_handler
|
2020-02-17 19:47:55 -08:00 |
|
felsabbagh3
|
3a45375596
|
Fixed Verilator
|
2020-02-17 19:36:00 -08:00 |
|