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61803741f82984f3d76fe2c5c455cc034ecfa640
vortex/rtl
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wgulian3 61803741f8 Merge branch 'master' into fpga_synthesis 
# Conflicts:
#	rtl/VX_back_end.v
#	rtl/VX_gpr_stage.v
#	rtl/VX_writeback.v
#	rtl/simulate/test_bench.cpp
#	rtl/simulate/test_bench.h
#	runtime/mains/dev/Makefile
2020-02-18 03:34:38 -05:00
..
cache
Cleanup imports of VX_define
2020-02-04 10:57:32 -05:00
compat
Add compat divide module and tb
2020-02-04 10:59:05 -05:00
interfaces
Merge branch 'master' into fpga_synthesis
2020-02-18 03:34:38 -05:00
modelsim
8Warp 32Threads for GTCAD synthesis
2019-11-21 23:51:11 -05:00
pipe_regs
Warps/Threads Parameterization
2019-11-21 01:15:21 -05:00
quartus
timing analysis tcl
2020-01-28 04:09:00 -05:00
shared_memory
SystemVerilog tweaks to appease Quartus and make Quartus synthesis work
2020-01-24 06:10:24 -05:00
simulate
Added CSRs, some Load unit tests are failing
2020-02-17 22:22:27 -08:00
.DS_Store
New RF with Evaluation
2019-09-11 01:04:23 -04:00
byte_enabled_simple_dual_port_ram.v
Add ram async clear port fix for fpga RAM inference
2020-02-06 13:07:50 -05:00
Makefile
Support exec multi-cycle for div/mul
2020-02-13 13:17:46 -05:00
results.txt
CACHE FINALLY WORKING
2019-10-25 04:01:23 -04:00
Vortex.v
Merge branch 'master' into fpga_synthesis
2020-02-18 03:34:38 -05:00
VX_alu.v
Support exec multi-cycle for div/mul
2020-02-13 13:17:46 -05:00
VX_back_end.v
Merge branch 'master' into fpga_synthesis
2020-02-18 03:34:38 -05:00
VX_countones.v
Modelsim Makefile compile + simulate - DPI
2019-10-26 19:01:49 -04:00
VX_csr_data.v
Added CSRs, some Load unit tests are failing
2020-02-17 22:22:27 -08:00
VX_csr_handler.v
New Warp Scheduler + VCD Enable
2019-09-15 00:12:41 -04:00
VX_csr_pipe.v
Added CSRs, some Load unit tests are failing
2020-02-17 22:22:27 -08:00
VX_csr_wrapper.v
SystemVerilog tweaks to appease Quartus and make Quartus synthesis work
2020-01-24 06:10:24 -05:00
VX_decode.v
Added CSRs, some Load unit tests are failing
2020-02-17 22:22:27 -08:00
VX_define_synth.v
reverted to 4 thread configuration
2019-11-22 00:13:55 -05:00
VX_define.v
Fixed Verilator
2020-02-17 19:36:00 -08:00
VX_dmem_controller.v
Shared Memory Implemented
2019-11-13 10:06:13 -05:00
VX_execute_unit.v
Support exec multi-cycle for div/mul
2020-02-13 13:17:46 -05:00
VX_fetch.v
Before way logic change
2019-11-08 18:16:40 -05:00
VX_front_end.v
vecadd bug fixing + ebreak for termination
2019-11-15 14:18:45 -05:00
VX_generic_priority_encoder.v
Cleanup imports of VX_define
2020-02-04 10:57:32 -05:00
VX_generic_register.v
reset posedge
2019-10-21 11:34:12 -04:00
VX_generic_stack.v
Readded IPDOM stack + SPLIT/Join tested
2019-10-21 21:24:49 -04:00
VX_gpgpu_inst.v
SystemVerilog tweaks to appease Quartus and make Quartus synthesis work
2020-01-24 06:10:24 -05:00
VX_gpr_stage.v
Merge branch 'master' into fpga_synthesis
2020-02-18 03:34:38 -05:00
VX_gpr_wrapper.v
SystemVerilog tweaks to appease Quartus and make Quartus synthesis work
2020-01-24 06:10:24 -05:00
VX_gpr.v
8Warp 32Threads for GTCAD synthesis
2019-11-21 23:51:11 -05:00
VX_inst_multiplex.v
Merge branch 'master' into fpga_synthesis
2020-02-18 03:34:38 -05:00
VX_lsu_addr_gen.v
SystemVerilog tweaks to appease Quartus and make Quartus synthesis work
2020-01-24 06:10:24 -05:00
VX_lsu.v
SystemVerilog tweaks to appease Quartus and make Quartus synthesis work
2020-01-24 06:10:24 -05:00
VX_priority_encoder_w_mask.v
Cleanup imports of VX_define
2020-02-04 10:57:32 -05:00
VX_priority_encoder.v
Modelsim basic sim
2019-10-26 00:34:57 -04:00
VX_scheduler.v
Support exec multi-cycle for div/mul
2020-02-13 13:17:46 -05:00
VX_warp_scheduler.v
SystemVerilog tweaks to appease Quartus and make Quartus synthesis work
2020-01-24 06:10:24 -05:00
VX_warp.v
Cleanup imports of VX_define
2020-02-04 10:57:32 -05:00
VX_writeback.v
Merge branch 'master' into fpga_synthesis
2020-02-18 03:34:38 -05:00