Blaise Tine
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d4e7b28be8
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cache refactoring
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2021-01-17 00:18:56 -08:00 |
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Blaise Tine
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5b80484123
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minor updates
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2021-01-16 14:16:10 -08:00 |
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Blaise Tine
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a56ecb696d
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minor updates
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2021-01-16 14:05:47 -08:00 |
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Blaise Tine
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4f26228d50
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minor updates
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2021-01-16 05:33:28 -08:00 |
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Blaise Tine
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fcbf57b66a
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specialized shared memory module
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2021-01-16 04:41:58 -08:00 |
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Blaise Tine
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ad6e0b4e77
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sp_ram byteen fix
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2021-01-15 16:28:03 -08:00 |
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Blaise Tine
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7ae936c25f
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minor updates
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2021-01-14 23:06:03 -08:00 |
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Blaise Tine
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fe64c47f60
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ccip write fix
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2021-01-14 22:49:06 -08:00 |
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Blaise Tine
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f146178c2d
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minor updates
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2021-01-13 15:52:03 -08:00 |
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Blaise Tine
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0e1650e1c2
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bank deadlock fix
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2021-01-13 15:51:42 -08:00 |
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Blaise Tine
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79cc4d98e6
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bank deadlock fix
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2021-01-13 13:06:07 -08:00 |
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Blaise Tine
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464c4f4bd8
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minor updates
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2021-01-12 20:16:59 -08:00 |
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Blaise Tine
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f18ac24675
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afu reset fix
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2021-01-12 17:13:47 -08:00 |
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Blaise Tine
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b4b5d6f0ab
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minor updates
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2021-01-12 15:19:38 -08:00 |
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Blaise Tine
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adcd3ad521
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minor updates
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2021-01-12 12:06:48 -08:00 |
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Blaise Tine
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ceae724207
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minor updates
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2021-01-12 11:24:36 -08:00 |
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Blaise Tine
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fa5592be22
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minor updates
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2021-01-12 03:10:39 -08:00 |
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Blaise Tine
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7c4823e65c
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fixed GPR reset bug, fixed lsu dup loading, fixed riscv-tests
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2021-01-11 23:55:09 -08:00 |
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Blaise Tine
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50cfc48c0a
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minor fix
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2021-01-11 02:59:59 -08:00 |
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Blaise Tine
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ba743678dc
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duplicate load addresses optimization
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2021-01-11 01:58:04 -08:00 |
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Blaise Tine
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ea2b73d5b0
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adding opencl sgemm and vecadd command line options
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2021-01-10 22:47:25 -08:00 |
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Blaise Tine
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7e93d253f2
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minor update
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2021-01-10 22:03:23 -08:00 |
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Blaise Tine
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e770824d47
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fixed afu cci write bug, fixed profile cache write miss bug, fixed bram byteenable inferance
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2021-01-10 20:26:15 -08:00 |
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Blaise Tine
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06945533cf
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fixed l2/l3 caches related bugs
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2021-01-09 16:32:55 -08:00 |
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Blaise Tine
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5c83c594c1
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minor update
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2021-01-07 17:25:59 -08:00 |
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Blaise Tine
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ac2242b51f
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minor update
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2021-01-07 00:18:10 -08:00 |
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Blaise Tine
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4eb85dd97a
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minor update
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2021-01-06 23:37:24 -08:00 |
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Blaise Tine
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ba1082249a
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minor update
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2021-01-06 23:30:30 -08:00 |
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Blaise Tine
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82fa3b850e
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minor update
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2021-01-06 22:31:25 -08:00 |
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Blaise Tine
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8aea9cbe07
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minor update
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2021-01-06 21:39:15 -08:00 |
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Blaise Tine
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146c285aa0
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minor update
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2021-01-06 19:59:04 -08:00 |
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Blaise Tine
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2b8435471a
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speeding up simulation using dedicated full dpi-based FPU core
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2021-01-06 18:44:06 -08:00 |
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Blaise Tine
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2058718f0f
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minor updates
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2021-01-06 07:18:14 -08:00 |
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Blaise Tine
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31ff70fd4e
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minor updates
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2021-01-05 15:03:41 -08:00 |
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Blaise Tine
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846a4036d3
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minor update
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2021-01-05 05:46:20 -08:00 |
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Blaise Tine
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39bff921be
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cache bug fixes
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2021-01-05 05:04:49 -08:00 |
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Blaise Tine
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762b8e2e3e
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fixed cache mshr critical path
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2021-01-04 12:49:40 -05:00 |
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Blaise Tine
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9a077b97f3
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-01-03 23:11:06 -05:00 |
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Blaise Tine
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4d55118545
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cache pipeline optimization - moved tag access to stage0
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2021-01-03 23:10:41 -05:00 |
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Blaise Tine
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4bc3b537bd
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fixed reset fan-out
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2021-01-03 20:06:36 -08:00 |
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Blaise Tine
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9cef1aae04
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cache fill response address is the mshr's top address, no need to store it
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2021-01-03 00:57:24 -05:00 |
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Blaise Tine
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4815ab099c
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using single-port block ram for cache tags, restoring core reset signal
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2021-01-02 19:53:41 -08:00 |
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Blaise Tine
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a766c16ac9
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opencl kernels update
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2021-01-02 16:49:06 -05:00 |
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Blaise Tine
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a825941f51
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-01-02 16:06:09 -05:00 |
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Blaise Tine
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2d69ca5d67
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scratchpad optimization for stack access using custom bank offset aligned to stack size
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2021-01-02 16:00:00 -05:00 |
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Blaise Tine
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93c36273fa
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minor update
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2021-01-01 20:24:18 -08:00 |
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Blaise Tine
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da9649c2a3
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fixed pipe register reset issue in synthesis
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2021-01-01 14:54:18 -08:00 |
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Blaise Tine
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c5cf494e72
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-01-01 11:46:45 -08:00 |
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Blaise Tine
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36602cfa6a
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buffering core reset signal
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2021-01-01 11:46:30 -08:00 |
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Blaise Tine
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30d950ada2
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vx_spawn_warps redesign using opencl's style scheduler
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2021-01-01 14:13:48 -05:00 |
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