Commit Graph

256 Commits

Author SHA1 Message Date
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d42171d2ed Merge branch 'master' into graphics 2021-05-26 23:33:06 -07:00
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4c5104e96a fixed shared memory multi-tag requests bug 2021-05-26 15:03:48 -07:00
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d8517d4d08 minor update 2021-05-26 13:37:07 -07:00
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244f4b0964 fixed shared memory write bug 2021-05-23 10:57:58 -07:00
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04a1c0e9eb IN_ORDER_MEM feature doesn't work becasue when cache bank's mem-req-queue is full, we need to schedule the mem response and skip the mshr 2021-05-01 13:44:08 -07:00
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8410c49f53 code refactoring: DRAM => MEM renaming 2021-04-26 00:58:48 -07:00
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d808aa2735 perf counters generic size 2021-04-25 21:15:24 -07:00
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4cb98a25a7 enabling 128-bit dram bus 2021-04-24 00:31:27 -04:00
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aff5903a22 minor ibuffer critical path optimization. 2021-04-19 20:53:13 -07:00
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d38d512d42 Merge remote-tracking branch 'origin/master' into graphics 2021-04-04 23:48:31 -07:00
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625689796f minor update 2021-04-04 23:42:57 -07:00
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87888a9a93 master merge fixes 2021-04-04 21:12:12 -07:00
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d6552a8851 minor update 2021-04-03 04:24:37 -07:00
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04a96e89c9 minor update 2021-04-01 12:34:18 -07:00
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0909ad3201 minor update 2021-03-20 21:57:06 -04:00
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1431ef9bc0 texunit tex_wrap 2021-03-20 13:40:42 -04:00
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062d02ddce Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2021-03-04 20:51:03 -08:00
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3f5fd6d394 using shiftreg-based skid buffers 2021-02-28 02:20:09 -08:00
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e64996946d using 44-bit perf counters - aligned with DSP counters width 2021-02-28 02:05:47 -08:00
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700f9eea19 moving MUL unit into ALU unit 2021-02-23 13:49:02 -08:00
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1346d64ba9 minor update 2021-02-22 04:04:13 -08:00
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7560202f8b cache bank refactoring - removing unecessary core response fifo & restoring single port data access 2021-02-21 21:47:46 -08:00
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ccb74ef286 cache data access with decoupled read/write ports 2021-02-21 15:18:24 -08:00
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05f93fac20 minor update 2021-02-20 13:15:15 -08:00
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9eed48435c instruction decode optimization 2021-02-14 00:19:54 -08:00
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3c37db877a cache specialization for in-order DRAM reponses 2021-02-13 20:23:29 -08:00
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ab63ac9e5d cache request interfaces update 2021-02-10 20:55:04 -08:00
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665b97b810 multi-ported cache support for streaming 2021-02-08 16:13:32 -08:00
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fd1726197b cache merge optimization 2021-02-07 07:33:39 -08:00
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111cc29482 minor update 2021-02-04 15:28:04 -08:00
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32b94f61f2 minor update 2021-02-01 11:00:09 -08:00
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62ff97d6e1 minor update - smem perf update 2021-02-01 10:29:20 -08:00
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dc18bfabb8 minor update - remove mshr data store 2021-01-30 06:40:48 -08:00
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5419859281 fcvt fix 2021-01-25 02:22:00 -08:00
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8775f63ec4 lkg build rollout with 16cores optimization on arria10 2021-01-24 16:49:22 -08:00
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74a687e395 minor updates 2021-01-18 05:43:30 -08:00
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b17f1109c6 minor updates 2021-01-18 04:34:34 -08:00
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a7f6b9fffc minor updates 2021-01-17 18:18:05 -08:00
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8b42393189 minor updates 2021-01-17 17:33:41 -08:00
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a046bd7a73 cache pipeline optimization 2021-01-17 17:19:52 -08:00
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ed216ab39d minor updates 2021-01-17 13:58:43 -08:00
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a69ba5ad7b cache flush support 2021-01-17 05:50:29 -08:00
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d4e7b28be8 cache refactoring 2021-01-17 00:18:56 -08:00
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5b80484123 minor updates 2021-01-16 14:16:10 -08:00
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a56ecb696d minor updates 2021-01-16 14:05:47 -08:00
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4f26228d50 minor updates 2021-01-16 05:33:28 -08:00
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fcbf57b66a specialized shared memory module 2021-01-16 04:41:58 -08:00
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f146178c2d minor updates 2021-01-13 15:52:03 -08:00
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0e1650e1c2 bank deadlock fix 2021-01-13 15:51:42 -08:00
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79cc4d98e6 bank deadlock fix 2021-01-13 13:06:07 -08:00