Blaise Tine
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ca46b0a0be
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OUTPUT_REG => OUT_REG renaming
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2021-09-09 03:05:38 -07:00 |
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c06efbf480
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minor update
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2021-09-07 23:47:41 -07:00 |
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0d91f8771e
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Workaround fix for Verilator bug with array indexing
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2021-09-07 23:28:54 -07:00 |
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d42baf34ff
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minor update
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2021-09-06 23:44:31 -07:00 |
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af1cecae07
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stream arbiter update
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2021-09-06 23:38:20 -07:00 |
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b52ace5142
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area optimization bundle
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2021-09-05 23:35:44 -07:00 |
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fe5112b6c1
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minor updates
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2021-09-05 23:05:21 -07:00 |
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377466ed1c
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fpu area optimization
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2021-09-05 21:01:52 -07:00 |
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f3ba27b138
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GPRs optimization - disabling BRAM's read-during-write bypass block.
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2021-08-28 15:34:36 -07:00 |
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28eb3cfdb2
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minor update
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2021-08-26 14:49:57 -07:00 |
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74a45e2772
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stream arbiter optimization (using indexing instead of onehot mux)
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2021-08-26 09:52:13 -07:00 |
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d91d56d126
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block ram refactoring (multi-porting supporting and simulation support)
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2021-08-26 08:19:44 -07:00 |
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e494860f38
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using lzc instead of priority_encoder
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2021-08-26 07:29:47 -07:00 |
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2a27bfbfd5
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LKG Build (reset network update -fmax=236 mhz 4c)
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2021-08-23 01:59:22 -07:00 |
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eef3dda81d
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fixed Verilator error
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2021-08-13 19:33:12 -07:00 |
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646371f9e9
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bram block optimization
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2021-08-13 19:31:55 -07:00 |
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f12be56d7c
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fixed Verilator warnings
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2021-08-13 05:52:43 -04:00 |
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7961cf7474
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Disabling tracing on library
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2021-08-12 01:55:52 -07:00 |
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7b8fe11e6a
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unused variables refactoring
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2021-08-05 01:46:26 -07:00 |
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79fd92a1b4
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minor update
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2021-07-30 17:43:15 -07:00 |
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160ff94a22
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minor update
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2021-07-30 16:01:22 -07:00 |
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3d19588e57
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bus arbiters refactoring
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2021-07-30 16:00:09 -07:00 |
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ea1e0f201e
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OUTPUT_REG refactoring
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2021-07-23 06:58:37 -07:00 |
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5c58f7eec6
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minor update
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2021-07-16 12:57:50 -07:00 |
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a8f9a2559d
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minor update
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2021-07-15 12:25:51 -07:00 |
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c5aec572b5
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minor update
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2021-07-15 11:46:43 -07:00 |
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7d01be367c
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reset network refactoring
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2021-07-15 11:34:55 -07:00 |
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22cf698e69
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minor update
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2021-07-13 05:25:44 -07:00 |
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10e9ee124b
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using onehot multiplexer to reduce critical path
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2021-07-08 00:26:59 -07:00 |
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dc34c5c5bd
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minor update
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2021-07-03 04:47:19 -07:00 |
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93fee18d59
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minor update
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2021-07-01 02:59:44 -07:00 |
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1ea738ed26
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lkg build
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2021-06-25 16:28:10 -07:00 |
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a3a7239b4d
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critical path optimizations
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2021-06-23 01:51:23 -07:00 |
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b8fd2308e1
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arbiter specialization
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2021-06-22 21:02:37 -07:00 |
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57143f5889
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synthesis optimizations
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2021-06-17 16:43:43 -07:00 |
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47c3234659
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minor update
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2021-06-13 10:58:48 -07:00 |
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Blaise Tine
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adf033b0aa
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non-cacheable memory address critical paths optimizations
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2021-06-10 12:47:18 -07:00 |
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aff5903a22
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minor ibuffer critical path optimization.
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2021-04-19 20:53:13 -07:00 |
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16bef8937b
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adding empty to index_buffer
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2021-03-30 10:15:42 -07:00 |
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b33a994f49
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minor update
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2021-03-29 23:51:05 -07:00 |
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bd40e7db70
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minor update - mux reordering to reduce critical path on input data
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2021-03-21 11:43:57 -07:00 |
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062d02ddce
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-03-04 20:51:03 -08:00 |
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3f5fd6d394
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using shiftreg-based skid buffers
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2021-02-28 02:20:09 -08:00 |
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ebee332e9d
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minor update
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2021-02-27 02:31:05 -08:00 |
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20d704b4d3
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skid buffer optimization
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2021-02-27 02:29:48 -08:00 |
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700f9eea19
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moving MUL unit into ALU unit
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2021-02-23 13:49:02 -08:00 |
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Blaise Tine
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143319d557
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minor optimization
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2021-02-18 16:03:16 -08:00 |
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Blaise Tine
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073964fdf7
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minor update
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2021-02-12 08:52:06 -08:00 |
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Blaise Tine
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72b6713a72
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updating fdiv/fsqrt bram hex files, reset_delay updaet
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2021-02-04 09:02:18 -08:00 |
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Blaise Tine
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5419859281
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fcvt fix
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2021-01-25 02:22:00 -08:00 |
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