Hansung Kim
bd67ff3439
Fix creating bogus mem reqs when commit is stalled
...
When commit stage is stalled, LSU ready is deasserted for mem writes
since stores commit immediately; however, the same was not applied to
valid, creating duplicate memory write requests. Fix by guarding both
ready and valid properly.
2024-03-13 20:43:27 -07:00
Hansung Kim
8317a3fbe5
Fix fence by disallowing x-initialization instead of all-0 mask
...
Setting mem_req_mask to all-zero triggers an assertion error in
mem_scheduler. Instead, disallow initialize-by-x in instruction decode
which is the source of x-propagation. Since this seems to only happen
in VCS, define-gate it accordingly.
This reverts commit a15f4fd483
2024-03-07 17:39:18 -08:00
Hansung Kim
010c4675ce
Fix undeclared mem_perf_if
2024-03-07 15:00:43 -08:00
Hansung Kim
b63333a4ec
Merge remote-tracking branch 'upstream/master' into vortex2
2024-03-07 14:45:48 -08:00
Hansung Kim
e7b0a149c7
Print TAG_ONLY_WIDTH of req_tag in trace
...
... for use in trace parser. Full req_tag includes debug information
that complicates matching request to a corresponding request by tag.
2024-03-04 21:10:59 -08:00
Blaise Tine
5f2b10b8a6
minor update
2024-02-09 21:20:23 -08:00
Blaise Tine
3fee1a6193
minor update
2024-02-09 20:34:44 -08:00
Blaise Tine
ae7b01405c
CI minor update
2024-02-08 14:10:00 -08:00
Blaise Tine
be0db6e1a5
minor update
2024-02-04 20:32:05 -08:00
Blaise Tine
50028c1a33
Merge remote-tracking branch 'origin' into develop
2024-02-04 20:19:30 -08:00
Blaise Tine
8d4b6c804f
minor update
2024-02-04 20:17:12 -08:00
Blaise Tine
6f7a389a1f
arbiters unlock refactoring
2024-02-04 20:16:18 -08:00
Blaise Tine
fe15647f98
minor update
2024-02-04 02:11:53 -08:00
Blaise Tine
b0b7cd2b1e
minor updates
2024-02-03 19:09:53 -08:00
Hansung Kim
eb63767051
Don't hardcode SIMULATION
2024-02-01 23:58:06 -08:00
Hansung Kim
48558982f7
Merge remote-tracking branch 'upstream/master' into vortex2
2024-02-01 23:35:58 -08:00
Hansung Kim
a15f4fd483
[BUGFIX] Set mem_req_mask to 0 for fence
...
Fence instructions have address field set to X's which propagates to
cache_req_ready, causing issue stalls. Fix this by setting req_mask to all-zero
so that they can be handled unaffected by x-propagation.
Setting req_valid to 0 does not fix the problem because the LSU only commits
instructions when they have a matching response coming back.
2024-02-01 22:44:33 -08:00
Blaise Tine
f9cd8be19e
minor update
2024-01-31 13:35:43 -08:00
Blaise Tine
dab262e4f7
Merge branch 'develop' of https://github.com/vortexgpgpu/vortex into develop
2024-01-31 12:03:50 -08:00
Blaise Tine
8ab7c590fd
disabling fetch's deadlock check when L1 caches are present
2024-01-31 06:16:54 -08:00
Blaise Tine
e2d1387df8
elastic buffers classification
2024-01-31 00:39:37 -08:00
Shinnung Jeong
fd65ed95eb
fix bug to access memory address in simx
2024-01-30 20:45:47 -05:00
Blaise Tine
b31d868a27
Merge branch 'develop'
2024-01-28 17:34:46 -08:00
Blaise Tine
b6919d19a7
minor update
2024-01-28 17:34:07 -08:00
Blaise Tine
6045597ad0
Merge branch 'develop'
2024-01-28 00:25:55 -08:00
Blaise Tine
1c1140d517
Merge branch 'develop' of https://github.com/vortexgpgpu/vortex into develop
2024-01-28 00:25:16 -08:00
Blaise Tine
38b92ad592
- using SV_DPI defines to disable DPI in synthesis-based simulations
...
- fixed Intel ASE run script: run_ase.sh
2024-01-28 00:22:21 -08:00
Hansung Kim
4643edf3e9
Properly determine core finish
2024-01-26 14:23:52 -08:00
Hansung Kim
c9d1275f0e
Define SIMULATION under VERILATOR
2024-01-25 23:23:34 -08:00
Hansung Kim
b9b675a288
Add VX_config.h
2024-01-25 23:23:17 -08:00
Hansung Kim
60d4180249
Increase LSUQ and IBUF size
2024-01-16 23:53:14 -08:00
lpc97667
a9d578f3ab
Docs update
2024-01-10 15:56:22 -05:00
Hansung Kim
62171c0788
Change dmem/smem width to LSU lanes not core lanes
2024-01-04 01:34:24 -08:00
Hansung Kim
fd425f1cdf
Change smem bundles into flattened 1-D arrays
2024-01-04 00:52:56 -08:00
Hansung Kim
e6f6d4ea06
Change dmem bundles into flattened 1-D arrays
2024-01-04 00:37:59 -08:00
Blaise Tine
f0e6a435f8
Merge branch 'develop'
2024-01-03 19:09:49 -08:00
Blaise Tine
648bf75b0b
minor update
2024-01-03 19:09:18 -08:00
Blaise Tine
3b75418ea9
Merge branch 'develop'
2024-01-03 10:24:48 -08:00
Blaise Tine
f2e8317412
updated documentation
2024-01-03 10:23:38 -08:00
Hansung Kim
ab55c04d0c
Add localparam for internal/external smem switch
2024-01-01 19:48:06 -08:00
Hansung Kim
b64f0c2794
Add if-stmt to switch between external/internal smem
2024-01-01 12:46:59 -08:00
Hansung Kim
22f656fec1
Add ports for smem TL and connect to smem bus
2024-01-01 02:22:49 -08:00
Hansung Kim
b6cc0c285e
Remove unused tilelink ports in VX_core_wrapper
2024-01-01 01:09:55 -08:00
Hansung Kim
144521e19c
Expose smem ports at VX_core top
...
smem_unit stays inside the core, and the two separate buses to dcache
and smem are exposed at VX_core.
Currently core_wrapper ties req valid to 1'b0, stalling kernels that
reads from sharedmem.
2023-12-31 23:57:31 -08:00
Blaise Tine
cc042a4098
Merge branch 'develop'
2023-12-31 15:30:20 -08:00
Blaise Tine
bd18b03cc3
minor update
2023-12-31 15:29:04 -08:00
Blaise Tine
e7f8b40d93
minor update
2023-12-31 11:46:41 -08:00
Blaise Tine
ec2a35def9
Merge branch 'develop'
2023-12-31 11:26:48 -08:00
Blaise Tine
031d24e695
minor updates
2023-12-30 00:52:44 -08:00
Hansung Kim
158624bc1b
Write operand to file in matmul kernel
2023-12-30 00:28:55 -08:00
