Blaise Tine
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7529f72c5d
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fixed OPAE crash, added custom bram module to controll rw collision, dogfood testcase argurment, optimzed buffered fifo, quartus build optimization flags
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2020-10-20 05:32:55 -07:00 |
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Blaise Tine
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32da50816f
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scope refactoring: adding modules definitions to VCD trace
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2020-10-12 23:26:02 -04:00 |
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Carter René Montgomery
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a83048b3bd
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Comments
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2020-10-06 14:50:56 -04:00 |
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Carter René Montgomery
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1f4af4777c
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Comments
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2020-10-06 14:35:46 -04:00 |
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Carter René Montgomery
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d2ab8d3cc6
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Added comments to prep for cache presentation
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2020-10-05 14:49:47 -04:00 |
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Blaise Tine
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4e1007e5b2
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scope refactoring
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2020-10-03 18:53:21 -04:00 |
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Blaise Tine
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f6f95e0c46
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mutiple fixes: parallel printf, fixed cycle in cache, opencl refactored vecadd and sgemm, regen opencl kernels with hard-float, fixed vortex io bus interface, fixed dpi floats APi to support multicore mode, make vlsim multicore default, make rtlsim multi-core default, removed POCL binaries from repository, updated Makefiles to use external POCL
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2020-09-19 14:45:42 -04:00 |
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Blaise Tine
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42e3b6c45d
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fixed lmp_mult parameters, ram init filepath
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2020-09-04 07:51:46 -07:00 |
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Blaise Tine
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31ffbe0d6a
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clean up 'stage_1_cycles' from cache
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2020-09-01 03:39:03 -07:00 |
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Blaise Tine
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af84e01856
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minor update
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2020-08-31 06:17:49 -07:00 |
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Blaise Tine
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0a0b28aac0
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minor update - 206-214 mhz
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2020-08-29 05:14:08 -07:00 |
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Blaise Tine
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f292e5003d
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quartus build fixes
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2020-08-23 22:04:46 -07:00 |
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Blaise Tine
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0b355f228e
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ibuffer addition
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2020-08-22 00:22:04 -07:00 |
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Blaise Tine
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6c12391338
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pipeline refactoring - fmax >= 222 mhz
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2020-08-14 21:50:14 -07:00 |
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Blaise Tine
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65415d2bbc
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getting dogfood tests passing on Verilator!
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2020-08-09 18:13:12 -04:00 |
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Blaise Tine
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cd29362d10
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fixed FPU handshake, optimized writeback's critical path
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2020-08-07 10:11:54 -07:00 |
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Blaise Tine
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31ee824862
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merged fpu_port branch
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2020-07-31 17:13:22 -04:00 |
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Blaise Tine
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4bdab8903e
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merge
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2020-07-31 16:49:59 -04:00 |
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Blaise Tine
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c9755a0c48
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lkg build with pipeline + FPU fixes
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2020-07-31 09:29:44 -04:00 |
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Blaise Tine
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c2dd0a8b39
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modelsim fixes && pipeline optimization
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2020-07-28 14:20:23 -07:00 |
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Blaise Tine
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7c86b68977
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pipeline refactoring: centralized issue buffer
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2020-07-26 11:21:08 -04:00 |
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Blaise Tine
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1f63f9da25
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new fpu implementation
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2020-07-24 00:00:37 -04:00 |
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Blaise Tine
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dc7efbcfb4
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pipeline refactoring
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2020-07-21 05:22:47 -04:00 |
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Blaise Tine
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577a5791dc
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pipeline refactoring
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2020-07-20 08:04:04 -04:00 |
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Blaise Tine
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25f66e6490
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pipeline refactoring
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2020-07-19 05:03:47 -04:00 |
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trmontgomery
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ed3a0cfa4d
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added rsp map
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2020-07-19 00:08:09 -04:00 |
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Blaise Tine
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bdfacf709c
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yosys synthesis refactoring
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2020-07-10 18:56:41 -04:00 |
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Blaise Tine
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77c3b2d45f
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lsu_unit refactoring to reduce critical path
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2020-07-10 11:23:34 -07:00 |
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Blaise Tine
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582a00d690
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adding OPAE CSR support
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2020-06-30 10:05:57 -07:00 |
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felsabbagh3
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14e4fd95b7
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Don't allow snrq scheduling if there's a valid reqq entry (Event if it can't be scheduled)
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2020-06-29 00:03:36 -07:00 |
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felsabbagh3
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21566cdcd7
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Fixed Single Core with Optimizations
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2020-06-28 19:38:36 -07:00 |
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felsabbagh3
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567376971e
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Added dram_fill_req_fast which is used to stall bank pipeline
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2020-06-28 15:22:36 -07:00 |
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felsabbagh3
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ffb760cf73
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Optimized cache writeback path by 1) VX_fair_arbiter and 2) Added a wb register between LSU and WB arbiter
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2020-06-28 14:27:47 -07:00 |
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felsabbagh3
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c95d3cb22b
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Added cache critical path optimizations
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2020-06-27 16:12:22 -07:00 |
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Blaise Tine
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baf7d3bb92
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minor update
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2020-06-27 17:46:45 -04:00 |
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Blaise Tine
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bc0c65dce7
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2020-06-27 13:56:44 -07:00 |
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Blaise Tine
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8302641510
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fpga fixes
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2020-06-27 14:03:20 -07:00 |
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Blaise Tine
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8a306de02d
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runtime static library
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2020-06-27 14:13:13 -04:00 |
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Blaise Tine
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0a01385a2c
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few updates
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2020-06-23 09:28:24 -07:00 |
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Blaise Tine
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d3440de403
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round robin arbiter + auto buffered queue + fixed dcache arbiter
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2020-06-20 17:56:04 -04:00 |
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Blaise Tine
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68d9fc9a75
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driver basic test and demo test refactoring
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2020-06-19 09:12:07 -07:00 |
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Blaise Tine
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d6b0ef2b3c
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scope refactoring + snoop invalidate
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2020-06-12 00:04:31 -07:00 |
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Blaise Tine
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c4f2488dbe
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
t
# the commit.
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2020-06-04 15:44:40 -07:00 |
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Blaise Tine
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4e0e710182
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OPAE rtl fixes
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2020-06-04 15:44:03 -07:00 |
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Blaise Tine
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171d46b501
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fix l2 cache issues
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2020-06-04 18:34:14 -04:00 |
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Blaise Tine
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ea890b457d
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fixed msrq regression
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2020-06-03 17:22:24 -04:00 |
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Blaise Tine
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04fc34b848
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minor update
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2020-06-03 03:05:45 -07:00 |
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Blaise Tine
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9b186dcc6e
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fixed L2 cache
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2020-06-02 05:32:50 -07:00 |
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Blaise Tine
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e01c411b20
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opae rtl fixes
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2020-06-01 23:06:13 -07:00 |
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Blaise Tine
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16d5a8a09c
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opae rtl fixes
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2020-05-31 14:51:42 -07:00 |
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