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b023496ecb
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minor update
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2021-03-01 03:00:58 -08:00 |
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c8af5a8f45
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minor update
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2021-03-01 02:56:58 -08:00 |
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ad06408044
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minor update
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2021-03-01 01:51:25 -08:00 |
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0e3872ee94
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floating-point CSR fix
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2021-03-01 01:46:41 -08:00 |
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b441870789
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rename use_imm and use_PC
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2021-03-01 00:38:46 -08:00 |
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013dab4aeb
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-02-28 19:12:30 -08:00 |
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41f09ffb55
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minor update - allow independent driver cleanup
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2021-02-28 18:19:26 -08:00 |
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a9cb0b4ec1
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minor update - asesim fix
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2021-02-28 17:30:21 -08:00 |
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e6bb8ccd94
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-02-28 17:21:19 -08:00 |
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c856cac8be
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-02-28 20:14:42 -05:00 |
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de0298ca47
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fsqrt replacement to newlib emulation
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2021-02-28 20:12:56 -05:00 |
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e3a11e4a5c
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minor fix
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2021-02-28 14:18:43 -08:00 |
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3f5fd6d394
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using shiftreg-based skid buffers
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2021-02-28 02:20:09 -08:00 |
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e64996946d
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using 44-bit perf counters - aligned with DSP counters width
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2021-02-28 02:05:47 -08:00 |
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Blaise Tine
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9fda618815
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minor typo
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2021-02-28 01:58:41 -08:00 |
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Blaise Tine
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8a9a67aa5a
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minor update
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2021-02-27 21:54:55 -08:00 |
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f5a17bd1a9
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decode optimization and refactoring
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2021-02-27 18:21:41 -08:00 |
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ebee332e9d
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minor update
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2021-02-27 02:31:05 -08:00 |
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Blaise Tine
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20d704b4d3
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skid buffer optimization
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2021-02-27 02:29:48 -08:00 |
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a8452483fe
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simX refactoring
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2021-02-27 02:27:19 -08:00 |
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4fe345f269
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adding floating extension to SimX
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2021-02-24 14:25:04 -08:00 |
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34ce0b8e89
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minor update
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2021-02-23 20:54:03 -08:00 |
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700f9eea19
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moving MUL unit into ALU unit
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2021-02-23 13:49:02 -08:00 |
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1792571e1b
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minor update
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2021-02-22 13:30:45 -08:00 |
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1346d64ba9
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minor update
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2021-02-22 04:04:13 -08:00 |
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f63ef8110c
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update opencl kernels
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2021-02-22 00:59:39 -05:00 |
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7560202f8b
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cache bank refactoring - removing unecessary core response fifo & restoring single port data access
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2021-02-21 21:47:46 -08:00 |
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ccb74ef286
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cache data access with decoupled read/write ports
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2021-02-21 15:18:24 -08:00 |
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3e961c4e6e
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minor update
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2021-02-21 15:14:46 -08:00 |
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6739dc7923
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minor update - registering execute units skid buffers
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2021-02-21 15:11:08 -08:00 |
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Blaise Tine
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f27c1fac5f
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minor update
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2021-02-21 03:38:24 -08:00 |
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Blaise Tine
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6d7692da37
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minor fix.
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2021-02-21 03:37:36 -08:00 |
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258eb633a6
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minor update
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2021-02-20 13:16:25 -08:00 |
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05f93fac20
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minor update
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2021-02-20 13:15:15 -08:00 |
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Blaise Tine
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143319d557
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minor optimization
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2021-02-18 16:03:16 -08:00 |
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31b3e380dc
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minor update
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2021-02-15 09:23:40 -08:00 |
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Blaise Tine
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9eed48435c
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instruction decode optimization
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2021-02-14 00:19:54 -08:00 |
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Blaise Tine
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3c37db877a
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cache specialization for in-order DRAM reponses
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2021-02-13 20:23:29 -08:00 |
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Blaise Tine
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4aaaebab6e
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minor update
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2021-02-12 10:18:57 -08:00 |
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Blaise Tine
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073964fdf7
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minor update
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2021-02-12 08:52:06 -08:00 |
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ab63ac9e5d
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cache request interfaces update
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2021-02-10 20:55:04 -08:00 |
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665b97b810
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multi-ported cache support for streaming
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2021-02-08 16:13:32 -08:00 |
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fd1726197b
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cache merge optimization
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2021-02-07 07:33:39 -08:00 |
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Blaise Tine
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6c1dc96626
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simX refactoring + removed oldRTL + CSR updates
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2021-02-06 12:52:54 -08:00 |
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Blaise Tine
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111cc29482
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minor update
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2021-02-04 15:28:04 -08:00 |
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Blaise Tine
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778453e43f
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remove unused code from kernel binaries, spawn_kernel optimization using shift instead of division
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2021-02-04 17:35:57 -05:00 |
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Blaise Tine
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3837638a85
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-02-04 15:15:41 -05:00 |
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Blaise Tine
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b047f589d6
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runtime instrinsics refactoring using RISC-V custom instruction assmebly directives
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2021-02-04 15:15:20 -05:00 |
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Blaise Tine
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6a6711b735
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minor update
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2021-02-04 09:11:46 -08:00 |
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Blaise Tine
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72b6713a72
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updating fdiv/fsqrt bram hex files, reset_delay updaet
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2021-02-04 09:02:18 -08:00 |
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