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809 Commits 7 Branches 0 Tags
adf8e7dcd54c660689c8c3ea6ad8915fb57b25f3
Commit Graph
56 Commits
Author SHA1 Message Date
felsabbagh3 9b989cec69 Fixed use before init 2020-04-04 18:41:25 -07:00
felsabbagh3 bcea9866a7 Fixed a couple of things 2020-04-04 18:20:06 -07:00
felsabbagh3 65fa9285bf Fixed Flushing and Prefetching 2020-04-04 17:57:35 -07:00
Blaise Tine 1f63139ce5 fix RTL code undefined variables 2020-04-03 22:59:40 -07:00
felsabbagh3 10e445d459 Provisioned Prefetching, currently disabled 2020-04-03 00:30:33 -07:00
felsabbagh3 7d1cc5234e Fixed dram_fill_accept dependant on input address 2020-04-02 20:26:37 -07:00
felsabbagh3 0e0b326b31 Removed bank Hazard Signals 2020-04-02 19:19:00 -07:00
felsabbagh3 1b9d9f3625 Fixed incorrect miss_add on pipeline stall 2020-03-31 20:23:09 -07:00
felsabbagh3 bcf894b581 Demo SOC W=8, T=4 Passing 2020-03-30 22:17:38 -07:00
felsabbagh3 66a837b0df SOC only 2 errors 2020-03-30 21:28:40 -07:00
felsabbagh3 36895d6e7c Fixed miss_add on for snoop replays 2020-03-29 21:21:53 -07:00
felsabbagh3 94cc2c10b1 Snoops shouldn't send fill requests 2020-03-29 19:16:00 -07:00
felsabbagh3 e31b2d6d7e Fixed pulling signals from different stages 2020-03-29 18:17:01 -07:00
felsabbagh3 d31116d584 Uses use_wb_valid instead of wb_req to include snoops 2020-03-29 17:59:10 -07:00
felsabbagh3 71aae3e0a9 .. 2020-03-29 17:28:57 -07:00
felsabbagh3 f96d77d75e Mismatched vs matched 2020-03-29 17:18:57 -07:00
felsabbagh3 a499bcd718 Added extra signals for debugging 2020-03-29 17:04:17 -07:00
felsabbagh3 95ee66f25a Fixed Snoop Invalidate Logic 2020-03-29 16:44:14 -07:00
felsabbagh3 73390b9f58 b/unb error 2020-03-29 16:09:48 -07:00
felsabbagh3 0a88c97485 Another reset issue... 2020-03-29 16:06:13 -07:00
felsabbagh3 eb6e0cee43 Fixing a bug in a fix... 2020-03-29 13:52:22 -07:00
felsabbagh3 cd418a1f96 Mrvq stopping reqq popping added to avoid mrvq full deadlock 2020-03-29 13:19:06 -07:00
felsabbagh3 f43a9ad1a6 Added proper resetting to cache 2020-03-29 10:57:32 -07:00
felsabbagh3 efac643c66 Added Proper Handshaking to Everything and Fixed a Couple of Bugs 2020-03-29 02:11:14 -07:00
felsabbagh3 313a8e3b4b All cache bugs fixed - Handshaking 2020-03-28 21:43:02 -07:00
felsabbagh3 5dc9493c61 ALL tests passing - handshake 2020-03-27 21:34:49 -07:00
felsabbagh3 614797e52f Migrating fpga_synthesis_temp to main 2020-03-27 13:15:23 -07:00
Blaise Tine 9621acff5b fixed Modelsim build errors 2020-03-26 03:54:23 -04:00
felsabbagh3 4e6de0dc38 Fixed most of the cache issues, mat_add left 2020-03-22 15:59:45 -07:00
felsabbagh3 d146070275 Fix for Single-Threaded 2020-03-22 14:44:46 -07:00
wgulian3 b1e77bec44 replace procedural continuous assignments and force MLAB inference for generic_queue_ll 2020-03-10 17:46:48 -04:00
wgulian3 372a1ad905 minor tweaks to appease quartus 
re-add fancy timing analysis scripts and revert to Makefile with custom quartus location support
 2020-03-10 12:15:30 -04:00
felsabbagh3 13c6cbfa5d L3 and CLUSTRING WORKS 2020-03-10 02:41:47 -07:00
felsabbagh3 cf0173ae15 Fixed Stall Pipeline Logic 2020-03-09 22:08:46 -07:00
felsabbagh3 e2ffbcf14b MULTICORE WITH L2 WORKING 2020-03-09 01:17:11 -07:00
felsabbagh3 b5b04a7070 Added Shared Memory 2020-03-08 15:00:53 -07:00
felsabbagh3 507d20f413 Cache Working on Mem Copy 2020-03-08 01:55:15 -08:00
felsabbagh3 f03f3fe037 Fixed all Cache Warnings 2020-03-07 14:34:05 -08:00
felsabbagh3 9bf0add937 Made the cache module configurable for multi-instantiation 2020-03-07 00:49:40 -08:00
felsabbagh3 fb23812e95 Added Lower Level Cache Hit Queue 2020-03-06 23:04:42 -08:00
felsabbagh3 44f6c68fe9 Got queue_ll to work by modifying when to update bypass 2020-03-06 22:50:20 -08:00
Blaise Tine 0816426662 added unit_test 2020-03-06 10:31:31 -05:00
Blaise Tine 9f5235dc3d added generic_queue_ll 2020-03-05 10:43:15 -05:00
Blaise Tine 9c56a10f15 synthesis fixes 2020-03-05 09:11:43 -05:00
Blaise Tine 33868512ac synthesis fixes 2020-03-05 07:03:23 -05:00
Blaise Tine 66a46f81ce synthesis fixes 2020-03-05 06:58:51 -05:00
felsabbagh3 457e8644f3 Added Snoop Invalidate/Writeback Req type 2020-03-05 01:30:16 -08:00
felsabbagh3 e0620a6f6a Added fill_invalidator 2020-03-04 23:55:02 -08:00
felsabbagh3 b038bdb491 New Cache Design Passing All Tests 2020-03-04 23:24:32 -08:00
felsabbagh3 b0b9b8238e Passing some cases 2020-03-04 04:05:54 -08:00