Added fill_invalidator

rtl/VX_cache/VX_bank.v

@@ -361,8 +361,21 @@ module VX_bank (
 	wire                             dwbq_empty;
 	wire                             dwbq_full;
 
+
+	wire invalidate_fill;
+	wire possible_fill = valid_st2 && miss_st2;
+	VX_fill_invalidator VX_fill_invalidator(
+		.clk               (clk),
+		.reset             (reset),
+		.possible_fill     (possible_fill),
+		.success_fill      (is_fill_st2),
+		.fill_addr         (addr_st2),
+		
+		.invalidate_fill   (invalidate_fill)
+		);
+
 	// Enqueu in dram_fill_req
-	assign dram_fill_req       = valid_st2 && miss_st2;
+	assign dram_fill_req       = valid_st2 && miss_st2 && !invalidate_fill;
 	assign dram_fill_req_addr  = addr_st2;
 
 	assign dram_wb_req = !dwbq_empty;

rtl/VX_cache/VX_cache_config.v

@@ -37,6 +37,10 @@
 	`define DWBQ_SIZE 4
 	// Dram Fill Req Queue Size
 	`define DFQQ_SIZE `REQQ_SIZE
+  // Fill Invalidator Active {Comment out define statement to invalidate}
+  `define FILL_INVALIDATOR_ACTIVE 1
+  // Fill Invalidator Size {Fill invalidator must be active}
+  `define FILL_INVALIDAOR_SIZE 16
 
 // Dram knobs
 	`define SIMULATED_DRAM_LATENCY_CYCLES 10

rtl/VX_cache/VX_fill_invalidator.v

@@ -0,0 +1,89 @@
+
+`include "VX_cache_config.v"
+
+module VX_fill_invalidator (
+	input  wire       clk,
+	input  wire       reset,
+
+	input  wire       possible_fill,
+	input  wire       success_fill,
+
+	input  wire[31:0] fill_addr,
+
+	output reg invalidate_fill
+	
+);
+
+
+	`ifndef FILL_INVALIDATOR_ACTIVE
+
+		assign invalidate_fill = 0;
+
+	`else 
+
+		reg[`FILL_INVALIDAOR_SIZE-1:0]         fills_active;
+		reg[`FILL_INVALIDAOR_SIZE-1:0][31:0]   fills_address;
+
+
+		reg                                         success_found;
+		reg[(`vx_clog2(`FILL_INVALIDAOR_SIZE))-1:0] success_index;
+
+		integer curr_fill;
+		always @(*) begin
+			assign invalidate_fill = 0;
+			assign success_found   = 0;
+			assign success_index   = 0;
+			for (curr_fill = 0; curr_fill < `FILL_INVALIDAOR_SIZE; curr_fill=curr_fill+1) begin
+
+				if (fill_addr[31:`LINE_SELECT_ADDR_START] == fills_address[curr_fill][31:`LINE_SELECT_ADDR_START]) begin
+					if (possible_fill && fills_active[curr_fill]) begin
+						assign invalidate_fill = 1;
+					end
+
+					if (success_fill) begin
+						assign success_found = 1;
+						assign success_index = curr_fill;
+					end
+				end
+			end
+		end
+
+
+
+
+	wire [(`vx_clog2(`FILL_INVALIDAOR_SIZE))-1:0] enqueue_index;
+	wire                                          enqueue_found;
+
+	VX_generic_priority_encoder #(.N(`FILL_INVALIDAOR_SIZE)) VX_sel_bank(
+		.valids(fills_active),
+		.index (enqueue_index),
+		.found (enqueue_found)
+		);
+
+
+	reg[`FILL_INVALIDAOR_SIZE-1:0] new_valids;
+
+
+
+	always @(posedge clk) begin
+		if (reset) begin
+			fills_active  <= 0;
+			fills_address <= 0;
+		end else begin
+			if (enqueue_found && !invalidate_fill) begin
+				fills_active[enqueue_index]  <= 1;
+				fills_address[enqueue_index] <= fill_addr;
+			end
+
+			if (success_found) begin
+				fills_active[success_index] <= 0;
+			end
+
+		end
+	end
+
+
+	`endif
+
+
+endmodule