 felsabbagh3
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db11bf6990
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Made the cache module configurable for multi-instantiation
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2020-03-07 00:49:40 -08:00 |
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felsabbagh3
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fb23812e95
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Added Lower Level Cache Hit Queue
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2020-03-06 23:04:42 -08:00 |
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felsabbagh3
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90d10f4b7d
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Added Lower Level Cache Hit Queue
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2020-03-06 23:04:42 -08:00 |
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felsabbagh3
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44f6c68fe9
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Got queue_ll to work by modifying when to update bypass
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2020-03-06 22:50:20 -08:00 |
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felsabbagh3
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2c616d8201
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Got queue_ll to work by modifying when to update bypass
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2020-03-06 22:50:20 -08:00 |
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Blaise Tine
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0816426662
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added unit_test
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2020-03-06 10:31:31 -05:00 |
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Blaise Tine
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abfd592fd2
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added unit_test
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2020-03-06 10:31:31 -05:00 |
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Blaise Tine
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9f5235dc3d
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added generic_queue_ll
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2020-03-05 10:43:15 -05:00 |
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Blaise Tine
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730c36ef18
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added generic_queue_ll
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2020-03-05 10:43:15 -05:00 |
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Blaise Tine
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9c56a10f15
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synthesis fixes
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2020-03-05 09:11:43 -05:00 |
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Blaise Tine
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721d22ae86
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synthesis fixes
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2020-03-05 09:11:43 -05:00 |
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Blaise Tine
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33868512ac
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synthesis fixes
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2020-03-05 07:03:23 -05:00 |
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Blaise Tine
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2ed98a4764
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synthesis fixes
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2020-03-05 07:03:23 -05:00 |
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Blaise Tine
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66a46f81ce
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synthesis fixes
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2020-03-05 06:58:51 -05:00 |
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Blaise Tine
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369c2c625c
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synthesis fixes
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2020-03-05 06:58:51 -05:00 |
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felsabbagh3
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457e8644f3
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Added Snoop Invalidate/Writeback Req type
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2020-03-05 01:30:16 -08:00 |
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felsabbagh3
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7222cdd199
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Added Snoop Invalidate/Writeback Req type
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2020-03-05 01:30:16 -08:00 |
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felsabbagh3
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e0620a6f6a
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Added fill_invalidator
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2020-03-04 23:55:02 -08:00 |
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felsabbagh3
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c257c0578e
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Added fill_invalidator
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2020-03-04 23:55:02 -08:00 |
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felsabbagh3
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b038bdb491
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New Cache Design Passing All Tests
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2020-03-04 23:24:32 -08:00 |
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felsabbagh3
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a86a403ca9
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New Cache Design Passing All Tests
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2020-03-04 23:24:32 -08:00 |
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felsabbagh3
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b0b9b8238e
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Passing some cases
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2020-03-04 04:05:54 -08:00 |
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felsabbagh3
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aa1a0ee376
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Passing some cases
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2020-03-04 04:05:54 -08:00 |
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felsabbagh3
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8f001ac6f2
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Added All Interfaces
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2020-03-03 22:48:49 -08:00 |
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felsabbagh3
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d8e25045be
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Added All Interfaces
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2020-03-03 22:48:49 -08:00 |
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felsabbagh3
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73cecd3866
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Added Core Interface
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2020-03-03 22:14:56 -08:00 |
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felsabbagh3
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01ae6ffafe
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Added Core Interface
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2020-03-03 22:14:56 -08:00 |
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felsabbagh3
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57a96e02b1
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Fixed some other timing issues
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2020-03-03 21:15:44 -08:00 |
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felsabbagh3
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58db00f555
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Fixed some other timing issues
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2020-03-03 21:15:44 -08:00 |
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felsabbagh3
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08986bf1dc
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Fixed incorrect valid and'ing in execute
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2020-03-03 20:57:20 -08:00 |
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felsabbagh3
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25b6dbdfa8
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Fixed incorrect valid and'ing in execute
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2020-03-03 20:57:20 -08:00 |
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felsabbagh3
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a47f7c11ec
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Finished cache, dram imp + interfaces left
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2020-03-03 19:42:33 -08:00 |
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felsabbagh3
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733d00aba9
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Finished cache, dram imp + interfaces left
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2020-03-03 19:42:33 -08:00 |
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felsabbagh3
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8ece8d8893
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Fixed miss reserv to support ST->LD sequences
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2020-03-03 17:04:39 -08:00 |
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felsabbagh3
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e2e053ff7b
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Fixed miss reserv to support ST->LD sequences
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2020-03-03 17:04:39 -08:00 |
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felsabbagh3
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80af320fdb
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Before fixing miss rsrv for ST->LD sequences
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2020-03-03 16:57:05 -08:00 |
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felsabbagh3
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b150327ca9
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Before fixing miss rsrv for ST->LD sequences
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2020-03-03 16:57:05 -08:00 |
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felsabbagh3
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361fc2c3fe
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Finished st0
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2020-03-03 02:49:30 -08:00 |
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felsabbagh3
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8784b09b18
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Finished st0
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2020-03-03 02:49:30 -08:00 |
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felsabbagh3
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3a970bbe7b
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Connected cache to bank
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2020-03-02 23:24:17 -08:00 |
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felsabbagh3
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8c6284f627
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Connected cache to bank
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2020-03-02 23:24:17 -08:00 |
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felsabbagh3
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fc5621cd1d
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Everything except bank internals
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2020-03-02 23:08:54 -08:00 |
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felsabbagh3
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f6cc05eaa2
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Everything except bank internals
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2020-03-02 23:08:54 -08:00 |
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felsabbagh3
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abca2f7abb
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Modified Scheduler to be mask based (allows thread granuility writebacks) + Fixed all LW and SW unit test errors errors
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2020-03-01 22:27:18 -08:00 |
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felsabbagh3
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d78338c7d4
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Modified Scheduler to be mask based (allows thread granuility writebacks) + Fixed all LW and SW unit test errors errors
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2020-03-01 22:27:18 -08:00 |
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felsabbagh3
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6bf25b5b78
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+Added icache stage -- 3rd case of AUIPC os broken?
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2020-03-01 18:01:02 -08:00 |
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felsabbagh3
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f98f5c414d
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+Added icache stage -- 3rd case of AUIPC os broken?
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2020-03-01 18:01:02 -08:00 |
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wgulian3
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23aabbf01d
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Make ALU div/mul pipelines longer and support logic element multiplication mode for better long pipeline performance
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2020-02-22 20:16:13 -05:00 |
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wgulian3
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ca61801199
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Make ALU div/mul pipelines longer and support logic element multiplication mode for better long pipeline performance
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2020-02-22 20:16:13 -05:00 |
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wgulian3
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b2afe526fe
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Update multiply for not SYN_FUNC
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2020-02-21 23:20:04 -05:00 |
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