 wgulian3
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123fb17723
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Remove VX_define.h and *_synth and runtime/config.h
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2020-03-26 04:07:17 -04:00 |
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Blaise Tine
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8fd742edd8
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fixed Modelsim build errors
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2020-03-26 03:56:44 -04:00 |
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Blaise Tine
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acafcceb94
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fixed Modelsim build errors
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2020-03-26 03:56:44 -04:00 |
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Blaise Tine
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9621acff5b
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fixed Modelsim build errors
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2020-03-26 03:54:23 -04:00 |
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Blaise Tine
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8aa2d74714
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fixed Modelsim build errors
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2020-03-26 03:54:23 -04:00 |
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Blaise Tine
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a7eb9a0c38
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code refactoring
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2020-03-26 03:20:46 -04:00 |
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Blaise Tine
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07c52d8729
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code refactoring
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2020-03-26 03:20:46 -04:00 |
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Blaise Tine
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4626389ee2
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code refactoring
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2020-03-26 01:41:01 -04:00 |
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Blaise Tine
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bf3d1fb5a2
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code refactoring
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2020-03-26 01:41:01 -04:00 |
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felsabbagh3
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4e6de0dc38
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Fixed most of the cache issues, mat_add left
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2020-03-22 15:59:45 -07:00 |
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felsabbagh3
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5372c07b01
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Fixed most of the cache issues, mat_add left
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2020-03-22 15:59:45 -07:00 |
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felsabbagh3
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d146070275
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Fix for Single-Threaded
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2020-03-22 14:44:46 -07:00 |
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felsabbagh3
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82ea79c680
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Fix for Single-Threaded
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2020-03-22 14:44:46 -07:00 |
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wgulian3
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902aa685b1
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Add threaded -O3 build mode
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2020-03-21 17:23:40 -04:00 |
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wgulian3
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10ebfd7e24
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Add threaded -O3 build mode
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2020-03-21 17:23:40 -04:00 |
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wgulian3
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1c82f9a11d
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revert saxpy change and fix stage_1_cycles not working
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2020-03-20 04:49:02 -04:00 |
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wgulian3
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f565d47844
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revert saxpy change and fix stage_1_cycles not working
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2020-03-20 04:49:02 -04:00 |
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wgulian3
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05b7ffff12
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Add modified RTL files for parameterized builds with VX_define_synth.v
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2020-03-20 04:04:15 -04:00 |
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wgulian3
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5b3df797a4
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Add modified RTL files for parameterized builds with VX_define_synth.v
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2020-03-20 04:04:15 -04:00 |
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felsabbagh3
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65f3ced608
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Fixed no L3 Verilator issues
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2020-03-13 15:11:20 -07:00 |
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felsabbagh3
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ff2fc5fa43
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Fixed no L3 Verilator issues
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2020-03-13 15:11:20 -07:00 |
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felsabbagh3
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fc94168e32
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Removed L3 for synthesis
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2020-03-13 15:01:46 -07:00 |
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felsabbagh3
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0f5528a229
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Removed L3 for synthesis
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2020-03-13 15:01:46 -07:00 |
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wgulian3
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dd2c9cd9d7
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Add power analysis Make target
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2020-03-12 13:14:50 -04:00 |
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wgulian3
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07ed4085ae
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Add power analysis Make target
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2020-03-12 13:14:50 -04:00 |
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wgulian3
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b1e77bec44
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replace procedural continuous assignments and force MLAB inference for generic_queue_ll
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2020-03-10 17:46:48 -04:00 |
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wgulian3
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c5fe43724e
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replace procedural continuous assignments and force MLAB inference for generic_queue_ll
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2020-03-10 17:46:48 -04:00 |
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wgulian3
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372a1ad905
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minor tweaks to appease quartus
re-add fancy timing analysis scripts and revert to Makefile with custom quartus location support
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2020-03-10 12:15:30 -04:00 |
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wgulian3
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a931b588c2
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minor tweaks to appease quartus
re-add fancy timing analysis scripts and revert to Makefile with custom quartus location support
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2020-03-10 12:15:30 -04:00 |
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felsabbagh3
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13c6cbfa5d
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L3 and CLUSTRING WORKS
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2020-03-10 02:41:47 -07:00 |
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felsabbagh3
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ca62e57a0d
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L3 and CLUSTRING WORKS
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2020-03-10 02:41:47 -07:00 |
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felsabbagh3
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cf0173ae15
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Fixed Stall Pipeline Logic
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2020-03-09 22:08:46 -07:00 |
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felsabbagh3
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dea271eb6b
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Fixed Stall Pipeline Logic
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2020-03-09 22:08:46 -07:00 |
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felsabbagh3
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e2ffbcf14b
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MULTICORE WITH L2 WORKING
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2020-03-09 01:17:11 -07:00 |
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felsabbagh3
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469334f23e
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MULTICORE WITH L2 WORKING
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2020-03-09 01:17:11 -07:00 |
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felsabbagh3
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a539630a0a
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Added Vortex SOC
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2020-03-08 15:24:21 -07:00 |
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felsabbagh3
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24f20a2da4
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Added Vortex SOC
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2020-03-08 15:24:21 -07:00 |
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felsabbagh3
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b5b04a7070
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Added Shared Memory
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2020-03-08 15:00:53 -07:00 |
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felsabbagh3
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6c52b3d09b
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Added Shared Memory
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2020-03-08 15:00:53 -07:00 |
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felsabbagh3
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b9a95631bc
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Icache stage mods + removed shared memory
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2020-03-08 14:04:55 -07:00 |
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felsabbagh3
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ec1aad1591
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Icache stage mods + removed shared memory
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2020-03-08 14:04:55 -07:00 |
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felsabbagh3
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2f94b26af0
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Icache working
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2020-03-08 13:59:35 -07:00 |
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felsabbagh3
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f315a8a44d
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Icache working
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2020-03-08 13:59:35 -07:00 |
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felsabbagh3
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507d20f413
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Cache Working on Mem Copy
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2020-03-08 01:55:15 -08:00 |
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felsabbagh3
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3b11e1d72f
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Cache Working on Mem Copy
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2020-03-08 01:55:15 -08:00 |
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felsabbagh3
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f03f3fe037
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Fixed all Cache Warnings
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2020-03-07 14:34:05 -08:00 |
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felsabbagh3
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4ed62f1aad
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Fixed all Cache Warnings
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2020-03-07 14:34:05 -08:00 |
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Blaise Tine
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3953a71180
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fixed write logic in generic_queue_ll
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2020-03-07 06:56:11 -05:00 |
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Blaise Tine
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ddafe96ca6
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fixed write logic in generic_queue_ll
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2020-03-07 06:56:11 -05:00 |
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felsabbagh3
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9bf0add937
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Made the cache module configurable for multi-instantiation
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2020-03-07 00:49:40 -08:00 |
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