Blaise Tine
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907e6868cd
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simx refactoring, fixed simple.hex, compatibility with rtlsim and vlsim complete, added to regression suite
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2021-03-08 23:58:33 -08:00 |
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Blaise Tine
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71e9745e68
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simx lkg build
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2021-03-08 08:34:02 -08:00 |
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Blaise Tine
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8eac091fb5
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simX floating-point fixes and refactoring
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2021-03-08 03:44:08 -08:00 |
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Blaise Tine
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062d02ddce
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-03-04 20:51:03 -08:00 |
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Blaise Tine
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8a86bddd3e
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fixed simX multicore support, added shared memory
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2021-03-04 20:45:27 -08:00 |
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Blaise Tine
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41f09ffb55
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minor update - allow independent driver cleanup
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2021-02-28 18:19:26 -08:00 |
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Blaise Tine
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e6bb8ccd94
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-02-28 17:21:19 -08:00 |
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Blaise Tine
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9fda618815
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minor typo
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2021-02-28 01:58:41 -08:00 |
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Blaise Tine
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a8452483fe
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simX refactoring
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2021-02-27 02:27:19 -08:00 |
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Blaise Tine
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700f9eea19
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moving MUL unit into ALU unit
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2021-02-23 13:49:02 -08:00 |
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Blaise Tine
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6c1dc96626
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simX refactoring + removed oldRTL + CSR updates
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2021-02-06 12:52:54 -08:00 |
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Blaise Tine
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778453e43f
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remove unused code from kernel binaries, spawn_kernel optimization using shift instead of division
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2021-02-04 17:35:57 -05:00 |
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Blaise Tine
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b047f589d6
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runtime instrinsics refactoring using RISC-V custom instruction assmebly directives
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2021-02-04 15:15:20 -05:00 |
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Blaise Tine
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a9f82bceae
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updating kernels with 32-cores support
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2021-01-25 10:33:42 -05:00 |
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Blaise Tine
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3602d287b4
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wspawn fix for small sets
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2021-01-25 07:04:54 -08:00 |
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Blaise Tine
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5419859281
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fcvt fix
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2021-01-25 02:22:00 -08:00 |
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Blaise Tine
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7ae936c25f
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minor updates
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2021-01-14 23:06:03 -08:00 |
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Blaise Tine
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fe64c47f60
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ccip write fix
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2021-01-14 22:49:06 -08:00 |
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Blaise Tine
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f18ac24675
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afu reset fix
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2021-01-12 17:13:47 -08:00 |
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Blaise Tine
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b4b5d6f0ab
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minor updates
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2021-01-12 15:19:38 -08:00 |
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Blaise Tine
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7c4823e65c
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fixed GPR reset bug, fixed lsu dup loading, fixed riscv-tests
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2021-01-11 23:55:09 -08:00 |
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Blaise Tine
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5c83c594c1
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minor update
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2021-01-07 17:25:59 -08:00 |
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Blaise Tine
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146c285aa0
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minor update
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2021-01-06 19:59:04 -08:00 |
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Blaise Tine
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2b8435471a
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speeding up simulation using dedicated full dpi-based FPU core
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2021-01-06 18:44:06 -08:00 |
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Blaise Tine
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39bff921be
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cache bug fixes
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2021-01-05 05:04:49 -08:00 |
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Blaise Tine
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762b8e2e3e
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fixed cache mshr critical path
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2021-01-04 12:49:40 -05:00 |
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Blaise Tine
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4bc3b537bd
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fixed reset fan-out
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2021-01-03 20:06:36 -08:00 |
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Blaise Tine
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4815ab099c
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using single-port block ram for cache tags, restoring core reset signal
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2021-01-02 19:53:41 -08:00 |
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Blaise Tine
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30d950ada2
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vx_spawn_warps redesign using opencl's style scheduler
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2021-01-01 14:13:48 -05:00 |
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Blaise Tine
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138db29310
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2020-12-31 22:40:34 -05:00 |
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Blaise Tine
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e4a00dd0d9
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fixed loader script stack setup
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2020-12-31 22:37:20 -05:00 |
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Blaise Tine
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abe32ed553
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cache optimization - moved read requests to stage1 and eliminating stage3
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2020-12-31 07:40:58 -08:00 |
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Blaise Tine
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d44144f72f
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FPU float<->int conversion optimization
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2020-12-29 15:37:45 -08:00 |
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Blaise Tine
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4f689c4ce9
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fixed global obejct sharing between cores
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2020-12-24 19:36:07 -05:00 |
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Blaise Tine
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703a861fe9
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added support for write-through cache, removed cache snooping support
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2020-12-23 23:51:02 -08:00 |
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Blaise Tine
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d956e268b9
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adding new performance counters (banks utilization and DRAM bus utilization)
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2020-12-22 12:33:45 -08:00 |
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Blaise Tine
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4bbd7bf408
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performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
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2020-12-19 02:45:06 -08:00 |
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Blaise Tine
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29cd2f5dff
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fixed register file initialization to zero synthesis inference
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2020-12-10 00:27:56 -08:00 |
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Blaise Tine
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707ba3760f
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minor update
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2020-12-08 21:37:53 -08:00 |
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Blaise Tine
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d5438fd591
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merging perf counters
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2020-12-08 21:02:39 -08:00 |
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Blaise Tine
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14baec86d5
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moved apae sources into rtl/afu
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2020-12-08 04:59:11 -08:00 |
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Blaise Tine
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d5fa82f5e4
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cache req datapath optimizations
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2020-12-08 02:58:08 -08:00 |
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Xandy Liu
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1595ff08e2
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PERF pipeline stalls and cache
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2020-12-08 01:14:41 -05:00 |
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Blaise Tine
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d68b32cd60
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minor update
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2020-12-06 22:40:27 -08:00 |
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Blaise Tine
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b7a724410b
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update DRAM simulation - reduce the latency of duplicate requests (simulate DRAM cache)
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2020-12-03 07:30:19 -08:00 |
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Blaise Tine
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b85391389b
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rename MSRQ to MSHR
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2020-11-28 17:32:00 -05:00 |
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Blaise Tine
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00d7473268
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build warnings clean
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2020-11-28 14:59:13 -05:00 |
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Blaise Tine
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461be0880d
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fixed FPU-CSR data dependence
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2020-11-25 09:05:38 -08:00 |
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Blaise Tine
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c04d385641
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minor update
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2020-11-23 20:12:04 -08:00 |
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Blaise Tine
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664ce28426
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minor update
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2020-11-23 12:21:39 -08:00 |
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