trmontgomery
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ed3a0cfa4d
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added rsp map
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2020-07-19 00:08:09 -04:00 |
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Blaise Tine
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bdfacf709c
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yosys synthesis refactoring
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2020-07-10 18:56:41 -04:00 |
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Blaise Tine
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77c3b2d45f
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lsu_unit refactoring to reduce critical path
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2020-07-10 11:23:34 -07:00 |
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Blaise Tine
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582a00d690
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adding OPAE CSR support
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2020-06-30 10:05:57 -07:00 |
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felsabbagh3
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14e4fd95b7
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Don't allow snrq scheduling if there's a valid reqq entry (Event if it can't be scheduled)
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2020-06-29 00:03:36 -07:00 |
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felsabbagh3
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21566cdcd7
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Fixed Single Core with Optimizations
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2020-06-28 19:38:36 -07:00 |
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felsabbagh3
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567376971e
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Added dram_fill_req_fast which is used to stall bank pipeline
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2020-06-28 15:22:36 -07:00 |
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felsabbagh3
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ffb760cf73
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Optimized cache writeback path by 1) VX_fair_arbiter and 2) Added a wb register between LSU and WB arbiter
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2020-06-28 14:27:47 -07:00 |
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felsabbagh3
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c95d3cb22b
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Added cache critical path optimizations
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2020-06-27 16:12:22 -07:00 |
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Blaise Tine
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baf7d3bb92
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minor update
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2020-06-27 17:46:45 -04:00 |
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Blaise Tine
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bc0c65dce7
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2020-06-27 13:56:44 -07:00 |
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Blaise Tine
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8302641510
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fpga fixes
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2020-06-27 14:03:20 -07:00 |
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Blaise Tine
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8a306de02d
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runtime static library
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2020-06-27 14:13:13 -04:00 |
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Blaise Tine
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0a01385a2c
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few updates
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2020-06-23 09:28:24 -07:00 |
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Blaise Tine
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d3440de403
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round robin arbiter + auto buffered queue + fixed dcache arbiter
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2020-06-20 17:56:04 -04:00 |
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Blaise Tine
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68d9fc9a75
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driver basic test and demo test refactoring
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2020-06-19 09:12:07 -07:00 |
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Blaise Tine
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d6b0ef2b3c
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scope refactoring + snoop invalidate
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2020-06-12 00:04:31 -07:00 |
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Blaise Tine
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c4f2488dbe
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
t
# the commit.
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2020-06-04 15:44:40 -07:00 |
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Blaise Tine
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4e0e710182
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OPAE rtl fixes
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2020-06-04 15:44:03 -07:00 |
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Blaise Tine
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171d46b501
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fix l2 cache issues
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2020-06-04 18:34:14 -04:00 |
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Blaise Tine
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ea890b457d
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fixed msrq regression
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2020-06-03 17:22:24 -04:00 |
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Blaise Tine
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04fc34b848
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minor update
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2020-06-03 03:05:45 -07:00 |
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Blaise Tine
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9b186dcc6e
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fixed L2 cache
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2020-06-02 05:32:50 -07:00 |
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Blaise Tine
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e01c411b20
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opae rtl fixes
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2020-06-01 23:06:13 -07:00 |
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Blaise Tine
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16d5a8a09c
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opae rtl fixes
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2020-05-31 14:51:42 -07:00 |
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Blaise Tine
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6a3b237054
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minor update
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2020-05-29 00:57:59 -04:00 |
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felsabbagh3
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033381ab6f
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Force correct word selection when BANK_LINE_WORD=1
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2020-05-28 20:39:39 -07:00 |
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Blaise Tine
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33b273b204
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-05-28 18:34:25 -04:00 |
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Blaise Tine
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b930a822ad
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minor updates
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2020-05-28 18:34:03 -04:00 |
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Blaise Tine
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611ceb000a
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fixed warp_sched lock bug
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2020-05-28 08:52:20 -04:00 |
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Blaise Tine
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9e5885b820
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adding dram writeenable support + scheduler bug fixes
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2020-05-27 19:00:23 -04:00 |
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Blaise Tine
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61231cd2af
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OPAE rtl fixes
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2020-05-24 02:42:56 -07:00 |
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Blaise Tine
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a9f896b4f3
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fixed snoop forwarding bug and single bank support
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2020-05-24 04:29:43 -04:00 |
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Blaise Tine
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47ed6b18ff
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-05-24 01:37:55 -04:00 |
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felsabbagh3
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a1e9b512b0
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Added mrvq_recover_ready_state_st2 to optimize fills sent
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2020-05-23 21:47:51 -07:00 |
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felsabbagh3
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0cd9bd689e
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Added schedule_ptr to mrvq for speculative pops
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2020-05-23 21:36:57 -07:00 |
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Blaise Tine
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3a9e79d979
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revert byte_enable tag structure
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2020-05-23 22:23:25 -04:00 |
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Blaise Tine
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c54fa50715
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fixed snoop forwarder dequue to support out of order responses
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2020-05-23 20:19:54 -04:00 |
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Blaise Tine
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6882d88a62
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removed fill_invalidator (not needed anymore)
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2020-05-23 19:24:52 -04:00 |
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Blaise Tine
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f3b21aab8f
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remove unsued cache parameter LLVQ_SIZE
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2020-05-23 00:33:51 -04:00 |
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Blaise Tine
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b02fc14da6
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fill invalifator fix + refactoring
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2020-05-21 20:38:55 -07:00 |
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Blaise Tine
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3c8620e770
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minor update
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2020-05-21 14:51:56 -04:00 |
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Blaise Tine
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cf22ef2bf3
|
minor update
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2020-05-21 13:42:08 -04:00 |
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felsabbagh3
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7e091b53f8
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Added valid_table in scheduler and removed rename_table on reset
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2020-05-20 23:02:41 -07:00 |
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Blaise Tine
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7e5fed3ec1
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-05-20 18:27:20 -04:00 |
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Blaise Tine
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72d54c749c
|
fixed cache msrq reset logic
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2020-05-20 18:11:31 -04:00 |
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Blaise Tine
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e1b4862f85
|
minor update
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2020-05-20 14:14:29 -07:00 |
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Blaise Tine
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cefd0d85af
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rtl refactoring
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2020-05-20 16:59:14 -04:00 |
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Blaise Tine
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b5569dd525
|
OPAE rtl fixes
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2020-05-20 12:08:10 -07:00 |
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Blaise Tine
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e269909db9
|
opae rtl fixes
|
2020-05-19 13:47:47 -07:00 |
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