wgulian3
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61803741f8
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Merge branch 'master' into fpga_synthesis
# Conflicts:
# rtl/VX_back_end.v
# rtl/VX_gpr_stage.v
# rtl/VX_writeback.v
# rtl/simulate/test_bench.cpp
# rtl/simulate/test_bench.h
# runtime/mains/dev/Makefile
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2020-02-18 03:34:38 -05:00 |
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felsabbagh3
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be66e51613
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Added CSRs, some Load unit tests are failing
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2020-02-17 22:22:27 -08:00 |
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wgulian3
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8318aff69f
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Support exec multi-cycle for div/mul
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2020-02-13 13:17:46 -05:00 |
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fares
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c09a15069b
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Improving critical path
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2019-11-18 13:11:05 -05:00 |
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fares
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c6d56f11c3
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Added EXEC to Warp Scheduler buffer
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2019-11-18 11:34:51 -05:00 |
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felsabbagh3
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3b49b82c46
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GPR ASIC Working
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2019-10-29 23:20:16 -04:00 |
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felsabbagh3
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01efe02e8b
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CACHE WORKING just needs lb/sb
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2019-10-25 03:03:09 -04:00 |
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felsabbagh3
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1e648c5819
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FIxed first circular issue
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2019-10-24 10:38:04 -04:00 |
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felsabbagh3
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1bfafca896
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Cleanup before integration
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2019-10-22 03:03:17 -04:00 |
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felsabbagh3
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121a985d12
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Reset to Generic Register
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2019-10-21 11:21:13 -04:00 |
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felsabbagh3
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84f5ccb484
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Added CSR TID/WID reads
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2019-10-21 02:10:05 -04:00 |
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felsabbagh3
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f7d826593f
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TMC working and tested
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2019-10-18 16:09:06 -04:00 |
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felsabbagh3
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f7b55427b4
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Added ISA2 infrastructure with bugs
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2019-10-18 05:21:32 -04:00 |
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felsabbagh3
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629ed3f8f9
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Before ISA2.0
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2019-10-18 04:15:34 -04:00 |
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felsabbagh3
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559c64cb36
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Cleanup
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2019-10-18 02:20:38 -04:00 |
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felsabbagh3
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505bbc20c8
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Removed FWD
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2019-10-18 02:01:39 -04:00 |
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felsabbagh3
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6779d0fade
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Instruction Multiplex LSU/EXU 1 cycle DONE
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2019-10-17 22:29:21 -04:00 |
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felsabbagh3
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95047fcadc
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Rename Stage that removes the need for forwarding
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2019-10-17 00:48:54 -04:00 |
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felsabbagh3
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ee83e6d8c8
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Moved GPR to back-end
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2019-10-14 19:08:32 -04:00 |
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felsabbagh3
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e67310acfb
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New Warp Scheduler + VCD Enable
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2019-09-15 00:12:41 -04:00 |
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felsabbagh3
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ecf81336db
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Finished FE and BE high-level
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2019-09-08 19:28:53 -04:00 |
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felsabbagh3
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981bf0afe5
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FE Done
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2019-09-08 18:36:47 -04:00 |
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