125 lines
3.1 KiB
Verilog
125 lines
3.1 KiB
Verilog
module VX_back_end (
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input wire clk,
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input wire reset,
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input wire fetch_delay,
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input wire[31:0] csr_decode_csr_data,
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output wire execute_branch_stall,
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output wire out_mem_delay,
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VX_jal_response_inter VX_jal_rsp,
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VX_branch_response_inter VX_branch_rsp,
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VX_frE_to_bckE_req_inter VX_bckE_req,
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VX_wb_inter VX_writeback_inter,
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VX_dcache_response_inter VX_dcache_rsp,
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VX_dcache_request_inter VX_dcache_req,
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VX_forward_exe_inter VX_fwd_exe,
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VX_forward_mem_inter VX_fwd_mem,
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VX_forward_wb_inter VX_fwd_wb,
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VX_csr_write_request_inter VX_csr_w_req
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);
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wire memory_delay;
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assign out_mem_delay = memory_delay;
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wire total_freeze = fetch_delay || memory_delay;
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wire[11:0] execute_csr_address;
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wire execute_is_csr;
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reg[31:0] execute_csr_result;
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wire execute_jal;
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wire[31:0] execute_jal_dest;
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VX_mw_wb_inter VX_mw_wb();
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VX_inst_mem_wb_inter VX_mem_wb();
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VX_mem_req_inter VX_exe_mem_req();
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VX_mem_req_inter VX_mem_req();
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VX_execute vx_execute(
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.VX_bckE_req (VX_bckE_req),
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.VX_fwd_exe (VX_fwd_exe),
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.in_csr_data (csr_decode_csr_data),
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.VX_exe_mem_req (VX_exe_mem_req),
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.out_csr_address (execute_csr_address),
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.out_is_csr (execute_is_csr),
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.out_csr_result (execute_csr_result),
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.out_jal (execute_jal),
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.out_jal_dest (execute_jal_dest),
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.out_branch_stall (execute_branch_stall)
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);
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assign VX_jal_rsp.jal_warp_num = VX_mem_req.warp_num;
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VX_e_m_reg vx_e_m_reg(
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.clk (clk),
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.reset (reset),
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.in_csr_address (execute_csr_address),
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.in_is_csr (execute_is_csr),
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.in_csr_result (execute_csr_result),
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.in_jal (execute_jal),
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.in_jal_dest (execute_jal_dest),
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.in_freeze (total_freeze),
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.VX_exe_mem_req (VX_exe_mem_req),
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.VX_mem_req (VX_mem_req),
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.out_csr_address (VX_csr_w_req.csr_address),
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.out_is_csr (VX_csr_w_req.is_csr),
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.out_csr_result (VX_csr_w_req.csr_result),
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.out_jal (VX_jal_rsp.jal),
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.out_jal_dest (VX_jal_rsp.jal_dest)
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);
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VX_memory vx_memory(
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.VX_mem_req (VX_mem_req),
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.VX_mem_wb (VX_mem_wb),
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.VX_fwd_mem (VX_fwd_mem),
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.out_delay (memory_delay),
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.VX_branch_rsp (VX_branch_rsp),
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.VX_dcache_rsp(VX_dcache_rsp),
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.VX_dcache_req (VX_dcache_req)
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);
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// VX_m_w_reg vx_m_w_reg(
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// .clk (clk),
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// .reset (reset),
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// .in_freeze (total_freeze),
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// .VX_mem_wb (VX_mem_wb),
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// .VX_mw_wb (VX_mw_wb)
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// );
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assign VX_mw_wb.alu_result = VX_mem_wb.alu_result;
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assign VX_mw_wb.mem_result = VX_mem_wb.mem_result;
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assign VX_mw_wb.rd = VX_mem_wb.rd;
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assign VX_mw_wb.wb = VX_mem_wb.wb;
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assign VX_mw_wb.PC_next = VX_mem_wb.PC_next;
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assign VX_mw_wb.valid = VX_mem_wb.valid;
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assign VX_mw_wb.warp_num = VX_mem_wb.warp_num;
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VX_writeback vx_writeback(
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.VX_mw_wb (VX_mw_wb),
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.VX_fwd_wb (VX_fwd_wb),
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.VX_writeback_inter(VX_writeback_inter)
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);
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endmodule |