felsabbagh3
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457e8644f3
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Added Snoop Invalidate/Writeback Req type
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2020-03-05 01:30:16 -08:00 |
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felsabbagh3
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e0620a6f6a
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Added fill_invalidator
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2020-03-04 23:55:02 -08:00 |
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felsabbagh3
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b038bdb491
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New Cache Design Passing All Tests
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2020-03-04 23:24:32 -08:00 |
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felsabbagh3
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b0b9b8238e
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Passing some cases
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2020-03-04 04:05:54 -08:00 |
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felsabbagh3
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8f001ac6f2
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Added All Interfaces
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2020-03-03 22:48:49 -08:00 |
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felsabbagh3
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73cecd3866
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Added Core Interface
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2020-03-03 22:14:56 -08:00 |
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felsabbagh3
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57a96e02b1
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Fixed some other timing issues
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2020-03-03 21:15:44 -08:00 |
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felsabbagh3
|
08986bf1dc
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Fixed incorrect valid and'ing in execute
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2020-03-03 20:57:20 -08:00 |
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felsabbagh3
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a47f7c11ec
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Finished cache, dram imp + interfaces left
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2020-03-03 19:42:33 -08:00 |
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felsabbagh3
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8ece8d8893
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Fixed miss reserv to support ST->LD sequences
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2020-03-03 17:04:39 -08:00 |
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felsabbagh3
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80af320fdb
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Before fixing miss rsrv for ST->LD sequences
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2020-03-03 16:57:05 -08:00 |
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felsabbagh3
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361fc2c3fe
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Finished st0
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2020-03-03 02:49:30 -08:00 |
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felsabbagh3
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3a970bbe7b
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Connected cache to bank
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2020-03-02 23:24:17 -08:00 |
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felsabbagh3
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fc5621cd1d
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Everything except bank internals
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2020-03-02 23:08:54 -08:00 |
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felsabbagh3
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abca2f7abb
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Modified Scheduler to be mask based (allows thread granuility writebacks) + Fixed all LW and SW unit test errors errors
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2020-03-01 22:27:18 -08:00 |
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felsabbagh3
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6bf25b5b78
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+Added icache stage -- 3rd case of AUIPC os broken?
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2020-03-01 18:01:02 -08:00 |
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wgulian3
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23aabbf01d
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Make ALU div/mul pipelines longer and support logic element multiplication mode for better long pipeline performance
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2020-02-22 20:16:13 -05:00 |
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wgulian3
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b2afe526fe
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Update multiply for not SYN_FUNC
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2020-02-21 23:20:04 -05:00 |
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wgulian3
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f2c0453702
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Add multi-cycle compat module and use it in ALU
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2020-02-21 22:08:09 -05:00 |
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wgulian3
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83d1f54fcf
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fix shared mem ram inference
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2020-02-20 15:59:23 -05:00 |
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wgulian3
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55d722364d
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Merge branch 'fpga_synthesis' into fix_cache_m10k
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2020-02-20 02:36:39 -05:00 |
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codetector
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e82e29c855
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remove async reset for FPGA synthesis
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2020-02-19 23:19:05 -05:00 |
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wgulian3
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de85cfd296
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fix clean build with makefile
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2020-02-19 17:33:51 -05:00 |
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Codetector
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072c89c433
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Merge branch 'fpga_synthesis' into fix_cache_m10k
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2020-02-19 16:03:23 -05:00 |
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wgulian3
|
5dadeffac8
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fix project.tcl
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2020-02-19 14:20:58 -05:00 |
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wgulian3
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3b60c10460
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Merge branch 'fpga_synthesis' of github.gatech.edu:casl/Vortex into fpga_synthesis
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2020-02-19 01:04:55 -05:00 |
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wgulian3
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3423e3189f
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Fix e2e building issues and increase division pipeline length
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2020-02-19 01:04:48 -05:00 |
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wgulian3
|
3e68c8bcf5
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verilator does not support delayed assignment in a loop
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2020-02-18 13:38:17 -05:00 |
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wgulian3
|
e76d05f7ce
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Fix issues quartus synthesis issues
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2020-02-18 13:24:18 -05:00 |
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wgulian3
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d71f8fcc73
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Fix divide edge case in verilator and move divide modules out of SYN_FUNC block within alu.
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2020-02-18 13:02:46 -05:00 |
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wgulian3
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a32d654263
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Merge branch 'master' into fpga_synthesis
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2020-02-18 03:35:12 -05:00 |
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wgulian3
|
61803741f8
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Merge branch 'master' into fpga_synthesis
# Conflicts:
# rtl/VX_back_end.v
# rtl/VX_gpr_stage.v
# rtl/VX_writeback.v
# rtl/simulate/test_bench.cpp
# rtl/simulate/test_bench.h
# runtime/mains/dev/Makefile
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2020-02-18 03:34:38 -05:00 |
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felsabbagh3
|
28ce40eebf
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fixed make w + vx_gpr_stage csr schedule
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2020-02-18 00:26:44 -08:00 |
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felsabbagh3
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be66e51613
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Added CSRs, some Load unit tests are failing
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2020-02-17 22:22:27 -08:00 |
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felsabbagh3
|
a0f3f67426
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Fixed double printing in ::io_handler
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2020-02-17 19:47:55 -08:00 |
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felsabbagh3
|
551c4aa2e9
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2020-02-17 19:36:17 -08:00 |
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felsabbagh3
|
3a45375596
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Fixed Verilator
|
2020-02-17 19:36:00 -08:00 |
|
Blaise Tine
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3aa4c26eb9
|
minor fix
|
2020-02-17 20:36:16 -05:00 |
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Blaise Tine
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90c3813340
|
fixed all C++ extra + pedantic errors
|
2020-02-17 15:02:06 -05:00 |
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wgulian3
|
4184980188
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verilator: run all riscv tests
|
2020-02-13 13:50:57 -05:00 |
|
wgulian3
|
e662ef4134
|
Fix verilator
|
2020-02-13 13:42:43 -05:00 |
|
wgulian3
|
86bfa4d1e4
|
Fix verilator
|
2020-02-13 13:18:06 -05:00 |
|
wgulian3
|
8318aff69f
|
Support exec multi-cycle for div/mul
|
2020-02-13 13:17:46 -05:00 |
|
codetector
|
ded06bcd12
|
ram m10k fix
|
2020-02-11 09:57:32 -05:00 |
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wgulian3
|
c1bd731d7f
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Add ram async clear port fix for fpga RAM inference
|
2020-02-06 13:07:50 -05:00 |
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wgulian3
|
9c7a9d88cf
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Replace div/rem expressions with divider modules in preparation for pipelining
|
2020-02-04 11:54:06 -05:00 |
|
wgulian3
|
0211ca4add
|
Add compat divide module and tb
|
2020-02-04 10:59:05 -05:00 |
|
wgulian3
|
8d20b52ea2
|
Cleanup imports of VX_define
|
2020-02-04 10:57:32 -05:00 |
|
Elsabbagh, Fares Ehab Mohamed Abouelnasr
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0e0ea52568
|
Merge pull request #1 from casl/OPAE
opae
|
2020-01-30 13:45:05 -08:00 |
|
Apurve Chawda
|
2eed4e68be
|
Create opae_setup.sh
|
2020-01-30 16:41:37 -05:00 |
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