Blaise Tine
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369c2c625c
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synthesis fixes
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2020-03-05 06:58:51 -05:00 |
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felsabbagh3
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25b6dbdfa8
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Fixed incorrect valid and'ing in execute
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2020-03-03 20:57:20 -08:00 |
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wgulian3
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8318aff69f
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Support exec multi-cycle for div/mul
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2020-02-13 13:17:46 -05:00 |
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wgulian3
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e9cdc6e5af
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SystemVerilog tweaks to appease Quartus and make Quartus synthesis work
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2020-01-24 06:10:24 -05:00 |
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Lyons, Ethan Tyler
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509850192c
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Warps/Threads Parameterization
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2019-11-21 01:14:50 -05:00 |
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fares
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c6d56f11c3
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Added EXEC to Warp Scheduler buffer
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2019-11-18 11:34:51 -05:00 |
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felsabbagh3
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58a9140f08
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Before evict_wb_old removal
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2019-11-07 13:27:38 -05:00 |
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felsabbagh3
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bbb2373919
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Intrinsics: tests for TMC+Control Divergence
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2019-11-01 21:53:37 -04:00 |
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felsabbagh3
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1181af1df2
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Modelsim basic sim
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2019-10-26 00:34:57 -04:00 |
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felsabbagh3
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1bfafca896
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Cleanup before integration
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2019-10-22 03:03:17 -04:00 |
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felsabbagh3
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b6375e76de
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Readded IPDOM stack + SPLIT/Join tested
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2019-10-21 21:24:49 -04:00 |
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felsabbagh3
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84f5ccb484
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Added CSR TID/WID reads
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2019-10-21 02:10:05 -04:00 |
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felsabbagh3
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559c64cb36
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Cleanup
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2019-10-18 02:20:38 -04:00 |
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felsabbagh3
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505bbc20c8
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Removed FWD
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2019-10-18 02:01:39 -04:00 |
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felsabbagh3
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6779d0fade
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Instruction Multiplex LSU/EXU 1 cycle DONE
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2019-10-17 22:29:21 -04:00 |
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