127 lines
4.3 KiB
Verilog
127 lines
4.3 KiB
Verilog
module VX_execute_unit (
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// input wire clk,
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// Input
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// Request
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VX_exec_unit_req_inter VX_exec_unit_req,
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// Output
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// Writeback
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VX_inst_exec_wb_inter VX_inst_exec_wb,
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// JAL Response
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VX_jal_response_inter VX_jal_rsp,
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// Branch Response
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VX_branch_response_inter VX_branch_rsp,
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input wire[31:0] in_csr_data,
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output wire[11:0] out_csr_address,
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output wire out_is_csr,
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output reg[31:0] out_csr_result
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);
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wire[`NT_M1:0][31:0] in_a_reg_data;
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wire[`NT_M1:0][31:0] in_b_reg_data;
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wire[4:0] in_alu_op;
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wire in_rs2_src;
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wire[31:0] in_itype_immed;
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wire[2:0] in_branch_type;
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wire[19:0] in_upper_immed;
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wire[31:0] in_csr_mask;
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wire in_jal;
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wire[31:0] in_jal_offset;
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wire[31:0] in_curr_PC;
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assign in_a_reg_data = VX_exec_unit_req.a_reg_data;
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assign in_b_reg_data = VX_exec_unit_req.b_reg_data;
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assign in_alu_op = VX_exec_unit_req.alu_op;
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assign in_rs2_src = VX_exec_unit_req.rs2_src;
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assign in_itype_immed = VX_exec_unit_req.itype_immed;
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assign in_branch_type = VX_exec_unit_req.branch_type;
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assign in_upper_immed = VX_exec_unit_req.upper_immed;
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assign in_csr_mask = VX_exec_unit_req.csr_mask;
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assign in_jal = VX_exec_unit_req.jal;
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assign in_jal_offset = VX_exec_unit_req.jal_offset;
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assign in_curr_PC = VX_exec_unit_req.curr_PC;
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wire[`NT_M1:0][31:0] alu_result;
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genvar index_out_reg;
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generate
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for (index_out_reg = 0; index_out_reg < `NT; index_out_reg = index_out_reg + 1)
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begin
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VX_alu vx_alu(
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// .in_reg_data (in_reg_data[1:0]),
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.in_1 (in_a_reg_data[index_out_reg]),
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.in_2 (in_b_reg_data[index_out_reg]),
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.in_rs2_src (in_rs2_src),
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.in_itype_immed(in_itype_immed),
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.in_upper_immed(in_upper_immed),
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.in_alu_op (in_alu_op),
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.in_csr_data (in_csr_data),
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.in_curr_PC (in_curr_PC),
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.out_alu_result(alu_result[index_out_reg])
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);
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end
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endgenerate
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reg temp_branch_dir;
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always @(*)
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begin
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case(VX_exec_unit_req.branch_type)
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`BEQ: temp_branch_dir = (alu_result[0] == 0) ? `TAKEN : `NOT_TAKEN;
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`BNE: temp_branch_dir = (alu_result[0] == 0) ? `NOT_TAKEN : `TAKEN;
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`BLT: temp_branch_dir = (alu_result[0][31] == 0) ? `NOT_TAKEN : `TAKEN;
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`BGT: temp_branch_dir = (alu_result[0][31] == 0) ? `TAKEN : `NOT_TAKEN;
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`BLTU: temp_branch_dir = (alu_result[0][31] == 0) ? `NOT_TAKEN : `TAKEN;
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`BGTU: temp_branch_dir = (alu_result[0][31] == 0) ? `TAKEN : `NOT_TAKEN;
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`NO_BRANCH: temp_branch_dir = `NOT_TAKEN;
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default: temp_branch_dir = `NOT_TAKEN;
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endcase // in_branch_type
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end
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wire[`NT_M1:0][31:0] duplicate_PC_data;
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genvar i;
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generate
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for (i = 0; i < `NT; i=i+1)
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begin
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assign duplicate_PC_data[i] = VX_exec_unit_req.PC_next;
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end
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endgenerate
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// Actual Writeback
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assign VX_inst_exec_wb.rd = VX_exec_unit_req.rd;
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assign VX_inst_exec_wb.wb = VX_exec_unit_req.wb;
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assign VX_inst_exec_wb.wb_valid = VX_exec_unit_req.valid;
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assign VX_inst_exec_wb.wb_warp_num = VX_exec_unit_req.warp_num;
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assign VX_inst_exec_wb.alu_result = VX_exec_unit_req.jal ? duplicate_PC_data : alu_result;
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// Jal rsp
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assign VX_jal_rsp.jal = in_jal;
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assign VX_jal_rsp.jal_dest = $signed(in_a_reg_data[0]) + $signed(in_jal_offset);
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assign VX_jal_rsp.jal_warp_num = VX_exec_unit_req.warp_num;
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// Branch rsp
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assign VX_branch_rsp.valid_branch = (VX_exec_unit_req.branch_type != `NO_BRANCH) && (|VX_exec_unit_req.valid);
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assign VX_branch_rsp.branch_dir = temp_branch_dir;
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assign VX_branch_rsp.branch_warp_num = VX_exec_unit_req.warp_num;
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assign VX_branch_rsp.branch_dest = $signed(VX_exec_unit_req.curr_PC) + ($signed(VX_exec_unit_req.itype_immed) << 1); // itype_immed = branch_offset
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always @(*) begin
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case(in_alu_op)
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`CSR_ALU_RW: out_csr_result = in_csr_mask;
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`CSR_ALU_RS: out_csr_result = in_csr_data | in_csr_mask;
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`CSR_ALU_RC: out_csr_result = in_csr_data & (32'hFFFFFFFF - in_csr_mask);
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default: out_csr_result = 32'hdeadbeef;
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endcase
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end
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assign out_is_csr = VX_exec_unit_req.is_csr;
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assign out_csr_address = VX_exec_unit_req.csr_address;
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endmodule |