Commit Graph

282 Commits

Author SHA1 Message Date
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104da0c238 kernels update 2021-06-11 06:21:25 -04:00
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3cc1190cd7 CSRs I/O refactoring 2021-06-11 03:08:07 -07:00
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ba4f705807 minor update 2021-06-06 14:04:15 -07:00
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ff911d7f8d minor update (renaming stress -> mstress) 2021-06-06 14:03:46 -07:00
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3071fb7a29 adding support for non-cacheable memory addressing 2021-06-06 13:35:55 -07:00
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84391c1a06 minor update 2021-06-04 20:46:34 -07:00
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df7d91d690 more testing 2021-05-26 15:29:39 -07:00
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b3e54e66f8 fixed compiler warnings 2021-05-23 10:54:06 -07:00
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3e88a71801 minor update 2021-05-06 08:55:46 -07:00
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bde6a69ea0 adding support for multi-banks memory bus 2021-05-04 07:32:03 -07:00
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bdbf99c5b0 minor update 2021-05-03 12:53:15 -07:00
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76f5531b58 adding stress test pre-built kernel 2021-05-03 12:44:36 -07:00
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ba16e88eab stress test update 2021-05-03 12:24:41 -07:00
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c1f40e081d adding stress test 2021-05-03 03:37:28 -07:00
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fc7c8e1639 driver tests updates 2021-05-02 12:12:59 -07:00
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d504adb236 afu mem controller refactoring 2021-05-01 08:39:52 -07:00
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95f057bc2e fpga build refactoring 2021-04-29 06:17:28 -07:00
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2216a3059d minor update 2021-04-27 05:52:01 -04:00
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64848788a1 minor update 2021-04-26 20:34:28 -07:00
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8543e3a8bf code refactoring 2021-04-26 02:34:21 -07:00
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8410c49f53 code refactoring: DRAM => MEM renaming 2021-04-26 00:58:48 -07:00
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0615e7481a minor update 2021-04-24 03:06:24 -04:00
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cad21a4b92 minor update 2021-04-24 01:17:38 -04:00
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4cb98a25a7 enabling 128-bit dram bus 2021-04-24 00:31:27 -04:00
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3a266fc792 adding compiler tests to regression suite 2021-03-09 05:01:56 -08:00
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ad11bdfc87 fix warnings 2021-03-09 04:58:00 -08:00
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c0abd6ef3f Aligned memory allocation workaround for PACE clusters 2021-03-09 03:25:45 -08:00
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66ea340d05 Fix RAM memory deallocation 2021-03-09 01:52:56 -08:00
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907e6868cd simx refactoring, fixed simple.hex, compatibility with rtlsim and vlsim complete, added to regression suite 2021-03-08 23:58:33 -08:00
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71e9745e68 simx lkg build 2021-03-08 08:34:02 -08:00
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8eac091fb5 simX floating-point fixes and refactoring 2021-03-08 03:44:08 -08:00
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062d02ddce Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2021-03-04 20:51:03 -08:00
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8a86bddd3e fixed simX multicore support, added shared memory 2021-03-04 20:45:27 -08:00
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41f09ffb55 minor update - allow independent driver cleanup 2021-02-28 18:19:26 -08:00
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e6bb8ccd94 Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2021-02-28 17:21:19 -08:00
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9fda618815 minor typo 2021-02-28 01:58:41 -08:00
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a8452483fe simX refactoring 2021-02-27 02:27:19 -08:00
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700f9eea19 moving MUL unit into ALU unit 2021-02-23 13:49:02 -08:00
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6c1dc96626 simX refactoring + removed oldRTL + CSR updates 2021-02-06 12:52:54 -08:00
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778453e43f remove unused code from kernel binaries, spawn_kernel optimization using shift instead of division 2021-02-04 17:35:57 -05:00
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b047f589d6 runtime instrinsics refactoring using RISC-V custom instruction assmebly directives 2021-02-04 15:15:20 -05:00
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a9f82bceae updating kernels with 32-cores support 2021-01-25 10:33:42 -05:00
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3602d287b4 wspawn fix for small sets 2021-01-25 07:04:54 -08:00
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5419859281 fcvt fix 2021-01-25 02:22:00 -08:00
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7ae936c25f minor updates 2021-01-14 23:06:03 -08:00
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fe64c47f60 ccip write fix 2021-01-14 22:49:06 -08:00
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f18ac24675 afu reset fix 2021-01-12 17:13:47 -08:00
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b4b5d6f0ab minor updates 2021-01-12 15:19:38 -08:00
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7c4823e65c fixed GPR reset bug, fixed lsu dup loading, fixed riscv-tests 2021-01-11 23:55:09 -08:00
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5c83c594c1 minor update 2021-01-07 17:25:59 -08:00