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fpga build refactoring

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This commit is contained in:
Blaise Tine
2021-04-29 06:17:28 -07:00
parent 2216a3059d
commit 95f057bc2e
16 changed files with 185 additions and 208 deletions
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5
driver/opae/vlsim/Makefile
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@@ -82,8 +82,9 @@ endif
VL_FLAGS += -DNOPAE
CFLAGS += -DNOPAE
# use DPI FPU
VL_FLAGS += -DFPU_DPI
# FPU backend
FPU_CORE ?= FPU_DPI
VL_FLAGS += -D$(FPU_CORE)
PROJECT = libopae-c-vlsim.so

5
driver/rtlsim/Makefile
View File

@@ -68,8 +68,9 @@ ifdef PERF
CFLAGS += -DPERF_ENABLE
endif
# use DPI FPU
VL_FLAGS += -DFPU_DPI
# FPU backend
FPU_CORE ?= FPU_DPI
VL_FLAGS += -D$(FPU_CORE)
PROJECT = libvortex.so
# PROJECT = libvortex.dylib