Blaise Tine
|
073964fdf7
|
minor update
|
2021-02-12 08:52:06 -08:00 |
|
Blaise Tine
|
72b6713a72
|
updating fdiv/fsqrt bram hex files, reset_delay updaet
|
2021-02-04 09:02:18 -08:00 |
|
Blaise Tine
|
5419859281
|
fcvt fix
|
2021-01-25 02:22:00 -08:00 |
|
Blaise Tine
|
8775f63ec4
|
lkg build rollout with 16cores optimization on arria10
|
2021-01-24 16:49:22 -08:00 |
|
Blaise Tine
|
ce9ef840d6
|
minor updates
|
2021-01-18 04:22:40 -08:00 |
|
Blaise Tine
|
9bce15a513
|
minor updates
|
2021-01-17 18:20:02 -08:00 |
|
Blaise Tine
|
1237a72536
|
minor updates
|
2021-01-17 18:11:42 -08:00 |
|
Blaise Tine
|
7e93d253f2
|
minor update
|
2021-01-10 22:03:23 -08:00 |
|
Blaise Tine
|
e770824d47
|
fixed afu cci write bug, fixed profile cache write miss bug, fixed bram byteenable inferance
|
2021-01-10 20:26:15 -08:00 |
|
Blaise Tine
|
146c285aa0
|
minor update
|
2021-01-06 19:59:04 -08:00 |
|
Blaise Tine
|
2b8435471a
|
speeding up simulation using dedicated full dpi-based FPU core
|
2021-01-06 18:44:06 -08:00 |
|
Blaise Tine
|
9f128085d5
|
scoreboard optimization - using writeback's end-of-packet status
|
2020-12-30 06:47:56 -08:00 |
|
Blaise Tine
|
e431162347
|
minor update
|
2020-12-30 04:09:21 -08:00 |
|
Blaise Tine
|
d44144f72f
|
FPU float<->int conversion optimization
|
2020-12-29 15:37:45 -08:00 |
|
Blaise Tine
|
e83c4638a0
|
FPU area optimization sharing fmadd hard block
|
2020-12-27 17:31:10 -08:00 |
|
Blaise Tine
|
25df233005
|
Adding Altera Stratix 10 support
|
2020-12-27 10:44:57 -08:00 |
|
Blaise Tine
|
b2b8f190dd
|
minor update
|
2020-12-26 14:47:41 -08:00 |
|
Blaise Tine
|
33c431ed44
|
multiplier unit optimization - using fifo for metadata, shift register optimization
|
2020-12-26 11:23:21 -08:00 |
|
Blaise Tine
|
4b7d871d62
|
allowing partial cache request submissions, io bus support broken
|
2020-12-21 03:53:13 -08:00 |
|
Blaise Tine
|
e0905f8352
|
minor update
|
2020-12-09 05:34:27 -08:00 |
|
Blaise Tine
|
d5438fd591
|
merging perf counters
|
2020-12-08 21:02:39 -08:00 |
|
Blaise Tine
|
13a5370254
|
register file refactoring
|
2020-12-05 01:40:50 -08:00 |
|
Blaise Tine
|
f3b1069ce8
|
adding stream arbiter
|
2020-12-03 06:40:23 -08:00 |
|
Blaise Tine
|
97739e9dcf
|
RAM blocks inference fixes
|
2020-11-30 14:02:47 -08:00 |
|
Blaise Tine
|
5758ef9ebf
|
generic_register reset network optimization
|
2020-11-29 18:41:36 -08:00 |
|
Blaise Tine
|
ac1883a13f
|
tabs cleanup
|
2020-11-28 17:08:01 -05:00 |
|
Blaise Tine
|
2d4fef6dd6
|
fixed fp_noncomp bug, ci toolchain script update, increased DRAM latency to 100 cycles
|
2020-11-23 11:59:40 -08:00 |
|
Blaise Tine
|
34b650be94
|
fixed shared memory addressing critical path, fixed VX_fp_noncomp output bug
|
2020-11-17 00:27:24 -08:00 |
|
Blaise Tine
|
725322807e
|
fixed DRAM response backpressure inside Cache
|
2020-11-10 05:24:57 -08:00 |
|
Blaise Tine
|
f6f95e0c46
|
mutiple fixes: parallel printf, fixed cycle in cache, opencl refactored vecadd and sgemm, regen opencl kernels with hard-float, fixed vortex io bus interface, fixed dpi floats APi to support multicore mode, make vlsim multicore default, make rtlsim multi-core default, removed POCL binaries from repository, updated Makefiles to use external POCL
|
2020-09-19 14:45:42 -04:00 |
|
Blaise Tine
|
36ec603d17
|
fpga fixes: warp scheduler, fnmadd, fdiv, fsqrt
|
2020-09-08 07:05:26 -07:00 |
|
Blaise Tine
|
75c98c6ea3
|
fmadd fix
|
2020-09-06 01:20:22 -07:00 |
|
Blaise Tine
|
42e3b6c45d
|
fixed lmp_mult parameters, ram init filepath
|
2020-09-04 07:51:46 -07:00 |
|
Blaise Tine
|
0a45a8beb3
|
minor update
|
2020-09-01 00:56:10 -07:00 |
|
Blaise Tine
|
4e8b9fb296
|
FPU SVDPI support complete
|
2020-09-01 00:59:37 -04:00 |
|
Blaise Tine
|
c1df08843c
|
minor update
|
2020-08-31 09:34:19 -04:00 |
|
Blaise Tine
|
c358226098
|
merge
|
2020-08-31 09:22:43 -04:00 |
|
Blaise Tine
|
df711986bc
|
FPU DPI fallback
|
2020-08-31 09:19:55 -04:00 |
|
Blaise Tine
|
af84e01856
|
minor update
|
2020-08-31 06:17:49 -07:00 |
|
Blaise Tine
|
0a0b28aac0
|
minor update - 206-214 mhz
|
2020-08-29 05:14:08 -07:00 |
|
Blaise Tine
|
b211b29670
|
removing pipeline additional registers
|
2020-08-25 14:02:35 -07:00 |
|
Blaise Tine
|
ee81e81818
|
adding using serial divider to save area cost
|
2020-08-25 02:29:27 -07:00 |
|
Blaise Tine
|
57971f6c76
|
decode op_mod optimization
|
2020-08-24 02:55:14 -07:00 |
|
Blaise Tine
|
f292e5003d
|
quartus build fixes
|
2020-08-23 22:04:46 -07:00 |
|
Blaise Tine
|
1c9445745f
|
fp_noncomp fixes
|
2020-08-23 16:53:28 -07:00 |
|
Blaise Tine
|
0b355f228e
|
ibuffer addition
|
2020-08-22 00:22:04 -07:00 |
|
Blaise Tine
|
6c12391338
|
pipeline refactoring - fmax >= 222 mhz
|
2020-08-14 21:50:14 -07:00 |
|
Blaise Tine
|
65415d2bbc
|
getting dogfood tests passing on Verilator!
|
2020-08-09 18:13:12 -04:00 |
|
Blaise Tine
|
cd29362d10
|
fixed FPU handshake, optimized writeback's critical path
|
2020-08-07 10:11:54 -07:00 |
|
Blaise Tine
|
ffd9515881
|
added altera fpu modules
|
2020-08-05 15:53:59 -07:00 |
|