Blaise Tine 33c431ed44 multiplier unit optimization - using fifo for metadata, shift register optimization

2020-12-26 11:23:21 -08:00

..

altera

allowing partial cache request submissions, io bus support broken

2020-12-21 03:53:13 -08:00

fpnew @ 1def7bb630

fpu implementation (part1)

2020-07-23 03:18:09 -07:00

svdpi

adding stream arbiter

2020-12-03 06:40:23 -08:00

VX_fp_addmul.v

multiplier unit optimization - using fifo for metadata, shift register optimization

2020-12-26 11:23:21 -08:00

VX_fp_div.v

multiplier unit optimization - using fifo for metadata, shift register optimization

2020-12-26 11:23:21 -08:00

VX_fp_fpga.v

tabs cleanup

2020-11-28 17:08:01 -05:00

VX_fp_ftoi.v

multiplier unit optimization - using fifo for metadata, shift register optimization

2020-12-26 11:23:21 -08:00

VX_fp_itof.v

multiplier unit optimization - using fifo for metadata, shift register optimization

2020-12-26 11:23:21 -08:00

VX_fp_madd.v

multiplier unit optimization - using fifo for metadata, shift register optimization

2020-12-26 11:23:21 -08:00

VX_fp_noncomp.v

register file refactoring

2020-12-05 01:40:50 -08:00

VX_fp_sqrt.v

multiplier unit optimization - using fifo for metadata, shift register optimization

2020-12-26 11:23:21 -08:00

VX_fp_type.v

tabs cleanup

2020-11-28 17:08:01 -05:00

VX_fpnew.v

merging perf counters

2020-12-08 21:02:39 -08:00