81 Commits

Author SHA1 Message Date
Blaise Tine
a671e1a05d moving submodules into third_party folder 2021-11-24 18:10:00 -05:00
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e380ded5e1 Merge branch 'master' into graphics 2021-10-15 19:32:11 -07:00
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b8682f56ac softfloat library integration 2021-10-10 13:20:50 -07:00
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29aba92bf1 minor update 2021-09-30 06:14:05 -07:00
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04249c3ee9 code refactoring for Vivado compatibility 2021-09-29 04:48:53 -04:00
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a45261b530 code refactoring for Vivado compatibility 2021-09-29 03:24:17 -04:00
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feca2db24e critical path optimizations 2021-09-15 04:50:45 -07:00
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5192846c72 minor updates 2021-09-10 02:57:05 -07:00
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3d052e9428 fmax optimization bundle (250 MHz). 2021-09-08 02:26:39 -07:00
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d42baf34ff minor update 2021-09-06 23:44:31 -07:00
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377466ed1c fpu area optimization 2021-09-05 21:01:52 -07:00
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a801a16062 instruction decode refactoring fixing naming collision 2021-08-29 20:07:34 -07:00
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eef3dda81d fixed Verilator error 2021-08-13 19:33:12 -07:00
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bb1ceffadd rebase master update 2021-07-30 21:03:14 -07:00
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69d8340e24 minor fpu bug fix 2021-07-16 12:50:45 -07:00
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7d01be367c reset network refactoring 2021-07-15 11:34:55 -07:00
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e2416aae45 reset network update 2021-07-13 05:19:39 -07:00
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25ef7d053c minor optimization 2021-07-13 05:03:17 -07:00
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360f8e4e37 reset network optimization 2021-07-01 18:05:59 -07:00
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d7bce5ab45 relaxing fcvt critical path 2021-06-22 09:34:35 -07:00
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d15e33e87f fpu dpi update 2021-03-31 02:36:34 -07:00
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09194a8501 minor update 2021-03-21 11:39:33 -07:00
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e85fa9d842 fixed FCVT timing critical path 2021-03-18 13:26:36 -07:00
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5e3a949d2d floating-point conversion fix 2021-03-01 06:11:03 -08:00
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073964fdf7 minor update 2021-02-12 08:52:06 -08:00
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72b6713a72 updating fdiv/fsqrt bram hex files, reset_delay updaet 2021-02-04 09:02:18 -08:00
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5419859281 fcvt fix 2021-01-25 02:22:00 -08:00
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8775f63ec4 lkg build rollout with 16cores optimization on arria10 2021-01-24 16:49:22 -08:00
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ce9ef840d6 minor updates 2021-01-18 04:22:40 -08:00
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9bce15a513 minor updates 2021-01-17 18:20:02 -08:00
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1237a72536 minor updates 2021-01-17 18:11:42 -08:00
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7e93d253f2 minor update 2021-01-10 22:03:23 -08:00
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e770824d47 fixed afu cci write bug, fixed profile cache write miss bug, fixed bram byteenable inferance 2021-01-10 20:26:15 -08:00
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146c285aa0 minor update 2021-01-06 19:59:04 -08:00
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2b8435471a speeding up simulation using dedicated full dpi-based FPU core 2021-01-06 18:44:06 -08:00
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9f128085d5 scoreboard optimization - using writeback's end-of-packet status 2020-12-30 06:47:56 -08:00
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e431162347 minor update 2020-12-30 04:09:21 -08:00
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d44144f72f FPU float<->int conversion optimization 2020-12-29 15:37:45 -08:00
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e83c4638a0 FPU area optimization sharing fmadd hard block 2020-12-27 17:31:10 -08:00
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25df233005 Adding Altera Stratix 10 support 2020-12-27 10:44:57 -08:00
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b2b8f190dd minor update 2020-12-26 14:47:41 -08:00
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33c431ed44 multiplier unit optimization - using fifo for metadata, shift register optimization 2020-12-26 11:23:21 -08:00
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4b7d871d62 allowing partial cache request submissions, io bus support broken 2020-12-21 03:53:13 -08:00
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e0905f8352 minor update 2020-12-09 05:34:27 -08:00
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d5438fd591 merging perf counters 2020-12-08 21:02:39 -08:00
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13a5370254 register file refactoring 2020-12-05 01:40:50 -08:00
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f3b1069ce8 adding stream arbiter 2020-12-03 06:40:23 -08:00
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97739e9dcf RAM blocks inference fixes 2020-11-30 14:02:47 -08:00
Blaise Tine
5758ef9ebf generic_register reset network optimization 2020-11-29 18:41:36 -08:00
Blaise Tine
ac1883a13f tabs cleanup 2020-11-28 17:08:01 -05:00