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adding stream arbiter

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This commit is contained in:
Blaise Tine
2020-12-03 06:40:23 -08:00
parent f575f16f57
commit f3b1069ce8
33 changed files with 717 additions and 745 deletions
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62
hw/rtl/libs/VX_fair_arbiter.v
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@@ -1,17 +1,20 @@
`include "VX_platform.vh"
module VX_fair_arbiter #(
parameter N = 1
parameter NUM_REQS = 1,
parameter LOCK_ENABLE = 0,
parameter LOG_NUM_REQS = $clog2(NUM_REQS)
) (
input wire clk,
input wire reset,
input wire [N-1:0] requests,
output wire [`LOG2UP(N)-1:0] grant_index,
output wire [N-1:0] grant_onehot,
output wire grant_valid
input wire clk,
input wire reset,
input wire [NUM_REQS-1:0] requests,
input wire enable,
output wire [LOG_NUM_REQS-1:0] grant_index,
output wire [NUM_REQS-1:0] grant_onehot,
output wire grant_valid
);
if (N == 1) begin
if (NUM_REQS == 1) begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
@@ -21,49 +24,40 @@ module VX_fair_arbiter #(
end else begin
reg [N-1:0] requests_use;
wire [N-1:0] update_value;
wire [N-1:0] late_value;
wire refill;
wire [N-1:0] refill_value;
reg [N-1:0] refill_original;
reg [NUM_REQS-1:0] remaining;
wire [NUM_REQS-1:0] remaining_next;
wire [NUM_REQS-1:0] requests_use;
reg use_buffer;
always @(posedge clk) begin
if (reset) begin
requests_use <= 0;
refill_original <= 0;
end else begin
if (refill) begin
requests_use <= refill_value;
refill_original <= refill_value;
end else begin
requests_use <= update_value;
end
remaining <= 0;
use_buffer <= 0;
end else if (!LOCK_ENABLE || enable) begin
remaining <= remaining_next;
use_buffer <= (remaining_next != 0);
end
end
end
assign refill = (requests_use == 0);
assign refill_value = requests;
assign requests_use = use_buffer ? remaining : requests;
reg [N-1:0] grant_onehot_r;
VX_priority_encoder #(
.N(N)
.N(NUM_REQS)
) priority_encoder (
.data_in (requests_use),
.data_out (grant_index),
.valid_out (grant_valid)
);
reg [NUM_REQS-1:0] grant_onehot_r;
always @(*) begin
grant_onehot_r = N'(0);
grant_onehot_r = NUM_REQS'(0);
grant_onehot_r[grant_index] = 1;
end
assign grant_onehot = grant_onehot_r;
assign late_value = ((refill_original ^ requests) & ~refill_original);
assign update_value = (requests_use & ~grant_onehot_r) | late_value;
assign remaining_next = requests_use & ~grant_onehot_r;
assign grant_onehot = grant_onehot_r;
end
endmodule

31
hw/rtl/libs/VX_fixed_arbiter.v
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@@ -1,20 +1,24 @@
`include "VX_platform.vh"
module VX_fixed_arbiter #(
parameter N = 1
parameter NUM_REQS = 1,
parameter LOCK_ENABLE = 0,
parameter LOG_NUM_REQS = $clog2(NUM_REQS)
) (
input wire clk,
input wire reset,
input wire [N-1:0] requests,
output wire [`LOG2UP(N)-1:0] grant_index,
output wire [N-1:0] grant_onehot,
output wire grant_valid
input wire clk,
input wire reset,
input wire [NUM_REQS-1:0] requests,
input wire enable,
output wire [LOG_NUM_REQS-1:0] grant_index,
output wire [NUM_REQS-1:0] grant_onehot,
output wire grant_valid
);
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
`UNUSED_VAR (enable)
if (N == 1) begin
if (NUM_REQS == 1) begin
assign grant_index = 0;
assign grant_onehot = requests;
@@ -22,22 +26,21 @@ module VX_fixed_arbiter #(
end else begin
reg [N-1:0] grant_onehot_r;
VX_priority_encoder # (
.N(N)
.N(NUM_REQS)
) priority_encoder (
.data_in (requests),
.data_out (grant_index),
.valid_out (grant_valid)
);
reg [NUM_REQS-1:0] grant_onehot_r;
always @(*) begin
grant_onehot_r = N'(0);
grant_onehot_r = NUM_REQS'(0);
grant_onehot_r[grant_index] = 1;
end
assign grant_onehot = grant_onehot_r;
assign grant_onehot = grant_onehot_r;
end
endmodule

2
hw/rtl/libs/VX_generic_queue.v
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@@ -154,7 +154,7 @@ module VX_generic_queue #(
.DATAW(DATAW),
.SIZE(SIZE),
.BUFFERED(0),
.RWCHECK(1),
.RWCHECK(0),
.FASTRAM(FASTRAM)
) dp_ram (
.clk(clk),

58
hw/rtl/libs/VX_matrix_arbiter.v
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@@ -1,17 +1,20 @@
`include "VX_platform.vh"
module VX_matrix_arbiter #(
parameter N = 1
parameter NUM_REQS = 1,
parameter LOCK_ENABLE = 0,
parameter LOG_NUM_REQS = $clog2(NUM_REQS)
) (
input wire clk,
input wire reset,
input wire [N-1:0] requests,
output wire [`LOG2UP(N)-1:0] grant_index,
output wire [N-1:0] grant_onehot,
output wire grant_valid
input wire clk,
input wire reset,
input wire [NUM_REQS-1:0] requests,
input wire enable,
output wire [LOG_NUM_REQS-1:0] grant_index,
output wire [NUM_REQS-1:0] grant_onehot,
output wire grant_valid
);
if (N == 1) begin
if (NUM_REQS == 1) begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
@@ -22,11 +25,12 @@ module VX_matrix_arbiter #(
end else begin
reg [N-1:1] state [N-1:0];
wire [N-1:0] pri [N-1:0];
reg [NUM_REQS-1:1] state [NUM_REQS-1:0];
wire [NUM_REQS-1:0] pri [NUM_REQS-1:0];
wire [NUM_REQS-1:0] grant_unqual;
for (genvar i = 0; i < N; i++) begin
for (genvar j = 0; j < N; j++) begin
for (genvar i = 0; i < NUM_REQS; i++) begin
for (genvar j = 0; j < NUM_REQS; j++) begin
if (j > i) begin
assign pri[j][i] = requests[i] && state[i][j];
end
@@ -37,28 +41,42 @@ module VX_matrix_arbiter #(
assign pri[j][i] = 0;
end
end
assign grant_onehot[i] = requests[i] && !(| pri[i]);
assign grant_unqual[i] = requests[i] && !(| pri[i]);
end
for (genvar i = 0; i < N; i++) begin
for (genvar j = i + 1; j < N; j++) begin
for (genvar i = 0; i < NUM_REQS; i++) begin
for (genvar j = i + 1; j < NUM_REQS; j++) begin
always @(posedge clk) begin
if (reset) begin
state[i][j] <= 0;
end else begin
state[i][j] <= (state[i][j] || grant_onehot[j]) && !grant_onehot[i];
state[i][j] <= (state[i][j] || grant_unqual[j]) && !grant_unqual[i];
end
end
end
end
if (LOCK_ENABLE == 0) begin
`UNUSED_VAR (enable)
assign grant_onehot = grant_unqual;
end else begin
reg [NUM_REQS-1:0] grant_unqual_prev;
always @(posedge clk) begin
if (reset) begin
grant_unqual_prev <= 0;
end else if (enable) begin
grant_unqual_prev <= grant_unqual;
end
end
assign grant_onehot = enable ? grant_unqual : grant_unqual_prev;
end
VX_onehot_encoder #(
.N(N)
.NUM_REQS(NUM_REQS)
) encoder (
.onehot (grant_onehot),
.onehot (grant_unqual),
`UNUSED_PIN (valid),
.value (grant_index)
.binary (grant_index)
);
assign grant_valid = (| requests);

2
hw/rtl/libs/VX_onehot_encooder.v
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@@ -11,7 +11,7 @@ module VX_onehot_encoder #(
reg valid_r;
always @(*) begin
binary_r = `LOG2UP(N)'(0);
binary_r = 'x;
valid_r = 1'b0;
for (integer i = 0; i < N; i++) begin
if (onehot[i]) begin

11
hw/rtl/libs/VX_priority_encoder.v
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@@ -1,11 +1,12 @@
`include "VX_platform.vh"
module VX_priority_encoder #(
parameter N = 1
parameter N = 1,
parameter LOGN = `LOG2UP(N)
) (
input wire [N-1:0] data_in,
output wire [`LOG2UP(N)-1:0] data_out,
output wire valid_out
input wire [N-1:0] data_in,
output wire [LOGN-1:0] data_out,
output wire valid_out
);
reg [`LOG2UP(N)-1:0] data_out_r;
@@ -13,7 +14,7 @@ module VX_priority_encoder #(
data_out_r = 0;
for (integer i = 0; i < N; i++) begin
if (data_in[i]) begin
data_out_r = `LOG2UP(N)'(i);
data_out_r = LOGN'(i);
break;
end
end

46
hw/rtl/libs/VX_rr_arbiter.v
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@@ -1,17 +1,20 @@
`include "VX_platform.vh"
module VX_rr_arbiter #(
parameter N = 1
parameter NUM_REQS = 1,
parameter LOCK_ENABLE = 0,
parameter LOG_NUM_REQS = $clog2(NUM_REQS)
) (
input wire clk,
input wire reset,
input wire [N-1:0] requests,
output wire [`LOG2UP(N)-1:0] grant_index,
output wire [N-1:0] grant_onehot,
output wire grant_valid
input wire clk,
input wire reset,
input wire [NUM_REQS-1:0] requests,
input wire enable,
output wire [LOG_NUM_REQS-1:0] grant_index,
output wire [NUM_REQS-1:0] grant_onehot,
output wire grant_valid
);
if (N == 1) begin
if (NUM_REQS == 1) begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
@@ -22,31 +25,34 @@ module VX_rr_arbiter #(
end else begin
reg [`CLOG2(N)-1:0] grant_table [N-1:0];
reg [`CLOG2(N)-1:0] state;
reg [N-1:0] grant_onehot_r;
reg [LOG_NUM_REQS-1:0] grant_table [NUM_REQS-1:0];
reg [LOG_NUM_REQS-1:0] state;
always @(*) begin
for (integer i = 0; i < N; i++) begin
grant_table[i] = `CLOG2(N)'(i);
for (integer j = 0; j < N; j++) begin
if (requests[(i+j) % N]) begin
grant_table[i] = `CLOG2(N)'((i+j) % N);
for (integer i = 0; i < NUM_REQS; i++) begin
grant_table[i] = LOG_NUM_REQS'(i);
for (integer j = 0; j < NUM_REQS; j++) begin
if (requests[(i+j) % NUM_REQS]) begin
grant_table[i] = LOG_NUM_REQS'((i+j) % NUM_REQS);
end
end
end
grant_onehot_r = N'(0);
grant_onehot_r[grant_table[state]] = 1;
end
always @(posedge clk) begin
if (reset) begin
state <= 0;
end else begin
end else if (!LOCK_ENABLE || enable) begin
state <= grant_table[state];
end
end
reg [NUM_REQS-1:0] grant_onehot_r;
always @(*) begin
grant_onehot_r = NUM_REQS'(0);
grant_onehot_r[grant_table[state]] = 1;
end
assign grant_index = grant_table[state];
assign grant_onehot = grant_onehot_r;
assign grant_valid = (| requests);

134
hw/rtl/libs/VX_stream_arbiter.v Normal file
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@@ -0,0 +1,134 @@
`include "VX_platform.vh"
module VX_stream_arbiter #(
parameter NUM_REQS = 1,
parameter DATAW = 1,
parameter TYPE = "F",
parameter BUFFERED = 0
) (
input wire clk,
input wire reset,
input wire [NUM_REQS-1:0] valid_in,
input wire [NUM_REQS-1:0][DATAW-1:0] data_in,
output wire [NUM_REQS-1:0] ready_in,
output wire valid_out,
output wire [DATAW-1:0] data_out,
input wire ready_out
);
localparam LOG_NUM_REQS = $clog2(NUM_REQS);
if (NUM_REQS == 1) begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
assign valid_out = valid_in;
assign data_out = data_in;
assign ready_in = ready_out;
end else begin
wire sel_enable;
wire sel_valid;
wire [LOG_NUM_REQS-1:0] sel_idx;
wire [NUM_REQS-1:0] sel_1hot;
if (TYPE == "X") begin
VX_fixed_arbiter #(
.NUM_REQS(NUM_REQS),
.LOCK_ENABLE(1)
) sel_arb (
.clk (clk),
.reset (reset),
.requests (valid_in),
.enable (sel_enable),
.grant_valid (sel_valid),
.grant_index (sel_idx),
.grant_onehot(sel_1hot)
);
end else if (TYPE == "R") begin
VX_rr_arbiter #(
.NUM_REQS(NUM_REQS),
.LOCK_ENABLE(1)
) sel_arb (
.clk (clk),
.reset (reset),
.requests (valid_in),
.enable (sel_enable),
.grant_valid (sel_valid),
.grant_index (sel_idx),
.grant_onehot(sel_1hot)
);
end else if (TYPE == "F") begin
VX_fair_arbiter #(
.NUM_REQS(NUM_REQS),
.LOCK_ENABLE(1)
) sel_arb (
.clk (clk),
.reset (reset),
.requests (valid_in),
.enable (sel_enable),
.grant_valid (sel_valid),
.grant_index (sel_idx),
.grant_onehot(sel_1hot)
);
end else if (TYPE == "M") begin
VX_matrix_arbiter #(
.NUM_REQS(NUM_REQS),
.LOCK_ENABLE(1)
) sel_arb (
.clk (clk),
.reset (reset),
.requests (valid_in),
.enable (sel_enable),
.grant_valid (sel_valid),
.grant_index (sel_idx),
.grant_onehot(sel_1hot)
);
end
if (BUFFERED) begin
wire stall = ~ready_out && valid_out;
assign sel_enable = ~stall;
VX_generic_register #(
.N(1 + DATAW),
.R(1)
) pipe_reg (
.clk (clk),
.reset (reset),
.stall (stall),
.flush (1'b0),
.in ({sel_valid, data_in[sel_idx]}),
.out ({valid_out, data_out})
);
for (genvar i = 0; i < NUM_REQS; i++) begin
assign ready_in[i] = sel_1hot[i] && ~stall;
end
end else begin
assign sel_enable = ready_out;
assign valid_out = sel_valid;
assign data_out = data_in[sel_idx];
for (genvar i = 0; i < NUM_REQS; i++) begin
assign ready_in[i] = sel_1hot[i] && ready_out;
end
end
end
endmodule