29 lines
614 B
Verilog
29 lines
614 B
Verilog
`include "VX_platform.vh"
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module VX_onehot_encoder #(
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parameter N = 6
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) (
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input wire [N-1:0] onehot,
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output wire [`LOG2UP(N)-1:0] binary,
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output wire valid
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);
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reg [`LOG2UP(N)-1:0] binary_r;
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reg valid_r;
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always @(*) begin
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binary_r = 'x;
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valid_r = 1'b0;
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for (integer i = 0; i < N; i++) begin
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if (onehot[i]) begin
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binary_r = `LOG2UP(N)'(i);
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valid_r = 1'b1;
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end
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end
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end
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assign binary = binary_r;
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assign valid = valid_r;
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endmodule
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