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yosys synthesis refactoring

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This commit is contained in:
Blaise Tine
2020-07-10 18:56:41 -04:00
parent 77c3b2d45f
commit bdfacf709c
28 changed files with 136 additions and 134 deletions
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2
driver/rtlsim/Makefile
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@@ -34,7 +34,7 @@ TOP = Vortex
SRCS = vortex.cpp ../common/vx_utils.cpp ../../hw/simulate/simulator.cpp SRCS = vortex.cpp ../common/vx_utils.cpp ../../hw/simulate/simulator.cpp
RTL_INCLUDE = -I../../hw/rtl -I../../hw/rtl/libs -I../../hw/rtl/interfaces -I../../hw/rtl/pipe_regs -I../../hw/rtl/cache RTL_INCLUDE = -I../../hw/rtl -I../../hw/rtl/libs -I../../hw/rtl/interfaces -I../../hw/rtl/cache
VL_FLAGS += --language 1800-2009 --assert -Wall -Wpedantic $(CONFIGS) VL_FLAGS += --language 1800-2009 --assert -Wall -Wpedantic $(CONFIGS)
VL_FLAGS += -Wno-DECLFILENAME VL_FLAGS += -Wno-DECLFILENAME

4
hw/modelsim/Makefile
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@@ -69,8 +69,8 @@ SRC = \
../rtl/cache/VX_generic_pe.v \ ../rtl/cache/VX_generic_pe.v \
../rtl/cache/cache_set.v \ ../rtl/cache/cache_set.v \
../rtl/cache/VX_cache_data_per_index.v \ ../rtl/cache/VX_cache_data_per_index.v \
../rtl/pipe_regs/VX_d_e_reg.v \ ../rtl/VX_d_e_reg.v \
../rtl/pipe_regs/VX_f_d_reg.v \ ../rtl/VX_f_d_reg.v \
../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v \ ../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v \
../models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.v \ ../models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.v \
../models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0.v \ ../models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0.v \

7
hw/opae/sources.txt
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@@ -103,10 +103,9 @@ QI:vortex_afu.qsf
../rtl/VX_inst_multiplex.v ../rtl/VX_inst_multiplex.v
../rtl/VX_dcache_arb.v ../rtl/VX_dcache_arb.v
../rtl/VX_mem_arb.v ../rtl/VX_mem_arb.v
../rtl/VX_f_d_reg.v
../rtl/pipe_regs/VX_f_d_reg.v ../rtl/VX_i_d_reg.v
../rtl/pipe_regs/VX_i_d_reg.v ../rtl/VX_d_e_reg.v
../rtl/pipe_regs/VX_d_e_reg.v
ccip_interface_reg.sv ccip_interface_reg.sv
ccip_std_afu.sv ccip_std_afu.sv

0
hw/rtl/pipe_regs/VX_d_e_reg.v → hw/rtl/VX_d_e_reg.v
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0
hw/rtl/pipe_regs/VX_f_d_reg.v → hw/rtl/VX_f_d_reg.v
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0
hw/rtl/pipe_regs/VX_i_d_reg.v → hw/rtl/VX_i_d_reg.v
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4
hw/rtl/VX_lsu_unit.v
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@@ -59,7 +59,7 @@ module VX_lsu_unit #(
wire [`NUM_THREADS-1:0][3:0] mem_req_byteen; wire [`NUM_THREADS-1:0][3:0] mem_req_byteen;
wire [`NUM_THREADS-1:0][31:0] mem_req_data; wire [`NUM_THREADS-1:0][31:0] mem_req_data;
for (i = 0; i < `NUM_THREADS; ++i) begin for (i = 0; i < `NUM_THREADS; i++) begin
assign mem_req_addr[i] = full_address[i][31:2]; assign mem_req_addr[i] = full_address[i][31:2];
assign mem_req_offset[i] = full_address[i][1:0]; assign mem_req_offset[i] = full_address[i][1:0];
assign mem_req_byteen[i] = wmask << full_address[i][1:0]; assign mem_req_byteen[i] = wmask << full_address[i][1:0];
@@ -148,7 +148,7 @@ module VX_lsu_unit #(
reg [`NUM_THREADS-1:0][31:0] core_rsp_data; reg [`NUM_THREADS-1:0][31:0] core_rsp_data;
wire [`NUM_THREADS-1:0][31:0] rsp_data_shifted; wire [`NUM_THREADS-1:0][31:0] rsp_data_shifted;
for (i = 0; i < `NUM_THREADS; ++i) begin for (i = 0; i < `NUM_THREADS; i++) begin
assign rsp_data_shifted[i] = dcache_rsp_if.data[i] >> {mem_rsp_offset[i], 3'b0}; assign rsp_data_shifted[i] = dcache_rsp_if.data[i] >> {mem_rsp_offset[i], 3'b0};
always @(*) begin always @(*) begin
case (core_rsp_mem_read) case (core_rsp_mem_read)

116
hw/rtl/Vortex.v
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@@ -139,54 +139,54 @@ module Vortex (
end else begin end else begin
wire [`NUM_CLUSTERS-1:0] per_cluster_dram_req_valid; wire per_cluster_dram_req_valid [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0] per_cluster_dram_req_rw; wire per_cluster_dram_req_rw [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0][`L2DRAM_BYTEEN_WIDTH-1:0] per_cluster_dram_req_byteen; wire [`L2DRAM_BYTEEN_WIDTH-1:0] per_cluster_dram_req_byteen [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0][`L2DRAM_ADDR_WIDTH-1:0] per_cluster_dram_req_addr; wire [`L2DRAM_ADDR_WIDTH-1:0] per_cluster_dram_req_addr [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0][`L2DRAM_LINE_WIDTH-1:0] per_cluster_dram_req_data; wire [`L2DRAM_LINE_WIDTH-1:0] per_cluster_dram_req_data [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0][`L2DRAM_TAG_WIDTH-1:0] per_cluster_dram_req_tag; wire [`L2DRAM_TAG_WIDTH-1:0] per_cluster_dram_req_tag [`NUM_CLUSTERS-1:0];
wire l3_core_req_ready; wire l3_core_req_ready;
wire [`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_valid; wire per_cluster_dram_rsp_valid [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0][`L2DRAM_LINE_WIDTH-1:0] per_cluster_dram_rsp_data; wire [`L2DRAM_LINE_WIDTH-1:0] per_cluster_dram_rsp_data [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0][`L2DRAM_TAG_WIDTH-1:0] per_cluster_dram_rsp_tag; wire [`L2DRAM_TAG_WIDTH-1:0] per_cluster_dram_rsp_tag [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_ready; wire per_cluster_dram_rsp_ready [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0] per_cluster_snp_req_valid; wire per_cluster_snp_req_valid [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0][`L2DRAM_ADDR_WIDTH-1:0] per_cluster_snp_req_addr; wire [`L2DRAM_ADDR_WIDTH-1:0] per_cluster_snp_req_addr [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0] per_cluster_snp_req_invalidate; wire per_cluster_snp_req_invalidate [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0][`L2SNP_TAG_WIDTH-1:0] per_cluster_snp_req_tag; wire [`L2SNP_TAG_WIDTH-1:0] per_cluster_snp_req_tag [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0] per_cluster_snp_req_ready; wire per_cluster_snp_req_ready [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0] per_cluster_snp_rsp_valid; wire per_cluster_snp_rsp_valid [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0][`L2SNP_TAG_WIDTH-1:0] per_cluster_snp_rsp_tag; wire [`L2SNP_TAG_WIDTH-1:0] per_cluster_snp_rsp_tag [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0] per_cluster_snp_rsp_ready; wire per_cluster_snp_rsp_ready [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0] per_cluster_io_req_valid; wire per_cluster_io_req_valid [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0] per_cluster_io_req_rw; wire per_cluster_io_req_rw [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0][3:0] per_cluster_io_req_byteen; wire [3:0] per_cluster_io_req_byteen [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0][29:0] per_cluster_io_req_addr; wire [29:0] per_cluster_io_req_addr [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0][31:0] per_cluster_io_req_data; wire [31:0] per_cluster_io_req_data [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0][`L2CORE_TAG_WIDTH-1:0] per_cluster_io_req_tag; wire [`L2CORE_TAG_WIDTH-1:0] per_cluster_io_req_tag [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0] per_cluster_io_req_ready; wire per_cluster_io_req_ready [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0] per_cluster_io_rsp_valid; wire per_cluster_io_rsp_valid [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0][`L2CORE_TAG_WIDTH-1:0] per_cluster_io_rsp_tag; wire [`L2CORE_TAG_WIDTH-1:0] per_cluster_io_rsp_tag [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0][31:0] per_cluster_io_rsp_data; wire [31:0] per_cluster_io_rsp_data [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0] per_cluster_io_rsp_ready; wire per_cluster_io_rsp_ready [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_req_valid; wire per_cluster_csr_io_req_valid [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0][11:0] per_cluster_csr_io_req_addr; wire [11:0] per_cluster_csr_io_req_addr [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_req_rw; wire per_cluster_csr_io_req_rw [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0][31:0] per_cluster_csr_io_req_data; wire [31:0] per_cluster_csr_io_req_data [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_req_ready; wire per_cluster_csr_io_req_ready [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_rsp_valid; wire per_cluster_csr_io_rsp_valid [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0][31:0] per_cluster_csr_io_rsp_data; wire [31:0] per_cluster_csr_io_rsp_data [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_rsp_ready; wire per_cluster_csr_io_rsp_ready [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0] per_cluster_busy; wire per_cluster_busy [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0] per_cluster_ebreak; wire per_cluster_ebreak [`NUM_CLUSTERS-1:0];
wire [`CLOG2(`NUM_CLUSTERS)-1:0] csr_io_request_id = `CLOG2(`NUM_CLUSTERS)'(csr_io_req_coreid >> `CLOG2(`NUM_CLUSTERS)); wire [`CLOG2(`NUM_CLUSTERS)-1:0] csr_io_request_id = `CLOG2(`NUM_CLUSTERS)'(csr_io_req_coreid >> `CLOG2(`NUM_CLUSTERS));
wire [`NC_BITS-1:0] per_cluster_csr_io_req_coreid = `NC_BITS'(csr_io_req_coreid); wire [`NC_BITS-1:0] per_cluster_csr_io_req_coreid = `NC_BITS'(csr_io_req_coreid);
@@ -336,27 +336,27 @@ module Vortex (
// L3 Cache /////////////////////////////////////////////////////////// // L3 Cache ///////////////////////////////////////////////////////////
wire [`L3NUM_REQUESTS-1:0] l3_core_req_valid; wire l3_core_req_valid [`L3NUM_REQUESTS-1:0];
wire [`L3NUM_REQUESTS-1:0] l3_core_req_rw; wire l3_core_req_rw [`L3NUM_REQUESTS-1:0];
wire [`L3NUM_REQUESTS-1:0][`L2DRAM_BYTEEN_WIDTH-1:0] l3_core_req_byteen; wire [`L2DRAM_BYTEEN_WIDTH-1:0] l3_core_req_byteen [`L3NUM_REQUESTS-1:0];
wire [`L3NUM_REQUESTS-1:0][`L2DRAM_ADDR_WIDTH-1:0] l3_core_req_addr; wire [`L2DRAM_ADDR_WIDTH-1:0] l3_core_req_addr [`L3NUM_REQUESTS-1:0];
wire [`L3NUM_REQUESTS-1:0][`L2DRAM_LINE_WIDTH-1:0] l3_core_req_data; wire [`L2DRAM_LINE_WIDTH-1:0] l3_core_req_data [`L3NUM_REQUESTS-1:0];
wire [`L3NUM_REQUESTS-1:0][`L2DRAM_TAG_WIDTH-1:0] l3_core_req_tag; wire [`L2DRAM_TAG_WIDTH-1:0] l3_core_req_tag [`L3NUM_REQUESTS-1:0];
wire [`L3NUM_REQUESTS-1:0] l3_core_rsp_valid; wire l3_core_rsp_valid [`L3NUM_REQUESTS-1:0];
wire [`L3NUM_REQUESTS-1:0][`L2DRAM_LINE_WIDTH-1:0] l3_core_rsp_data; wire [`L2DRAM_LINE_WIDTH-1:0] l3_core_rsp_data [`L3NUM_REQUESTS-1:0];
wire [`L3NUM_REQUESTS-1:0][`L2DRAM_TAG_WIDTH-1:0] l3_core_rsp_tag; wire [`L2DRAM_TAG_WIDTH-1:0] l3_core_rsp_tag [`L3NUM_REQUESTS-1:0];
wire l3_core_rsp_ready; wire l3_core_rsp_ready;
wire [`NUM_CLUSTERS-1:0] l3_snp_fwdout_valid; wire l3_snp_fwdout_valid [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0][`L2DRAM_ADDR_WIDTH-1:0] l3_snp_fwdout_addr; wire [`L2DRAM_ADDR_WIDTH-1:0] l3_snp_fwdout_addr [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0] l3_snp_fwdout_invalidate; wire l3_snp_fwdout_invalidate [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0][`L2SNP_TAG_WIDTH-1:0] l3_snp_fwdout_tag; wire [`L2SNP_TAG_WIDTH-1:0] l3_snp_fwdout_tag [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0] l3_snp_fwdout_ready; wire l3_snp_fwdout_ready [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0] l3_snp_fwdin_valid; wire l3_snp_fwdin_valid [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0][`L2SNP_TAG_WIDTH-1:0] l3_snp_fwdin_tag; wire [`L2SNP_TAG_WIDTH-1:0] l3_snp_fwdin_tag [`NUM_CLUSTERS-1:0];
wire [`NUM_CLUSTERS-1:0] l3_snp_fwdin_ready; wire l3_snp_fwdin_ready [`NUM_CLUSTERS-1:0];
for (i = 0; i < `L3NUM_REQUESTS; i++) begin for (i = 0; i < `L3NUM_REQUESTS; i++) begin
// Core Request // Core Request

2
hw/rtl/cache/VX_cache_miss_resrv.v vendored
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@@ -66,7 +66,7 @@ module VX_cache_miss_resrv #(
reg [`LOG2UP(MRVQ_SIZE+1)-1:0] size; reg [`LOG2UP(MRVQ_SIZE+1)-1:0] size;
`STATIC_ASSERT(MRVQ_SIZE > 5, "invalid size"); `STATIC_ASSERT(MRVQ_SIZE > 5, "invalid size")
assign miss_resrv_full = (size == $bits(size)'(MRVQ_SIZE)); assign miss_resrv_full = (size == $bits(size)'(MRVQ_SIZE));
assign miss_resrv_stop = (size > $bits(size)'(MRVQ_SIZE-5)); // need to add 5 cycles to prevent pipeline lock assign miss_resrv_stop = (size > $bits(size)'(MRVQ_SIZE-5)); // need to add 5 cycles to prevent pipeline lock

2
hw/rtl/cache/VX_snp_forwarder.v vendored
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@@ -37,7 +37,7 @@ module VX_snp_forwarder #(
input wire [NUM_REQUESTS-1:0][`LOG2UP(SNRQ_SIZE)-1:0] snp_fwdin_tag, input wire [NUM_REQUESTS-1:0][`LOG2UP(SNRQ_SIZE)-1:0] snp_fwdin_tag,
output wire [NUM_REQUESTS-1:0] snp_fwdin_ready output wire [NUM_REQUESTS-1:0] snp_fwdin_ready
); );
`STATIC_ASSERT(NUM_REQUESTS > 1, "invalid value"); `STATIC_ASSERT(NUM_REQUESTS > 1, "invalid value")
reg [`REQS_BITS:0] pending_cntrs [SNRQ_SIZE-1:0]; reg [`REQS_BITS:0] pending_cntrs [SNRQ_SIZE-1:0];

10
hw/rtl/libs/VX_divide.v
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@@ -10,11 +10,11 @@ module VX_divide #(
input wire clk, input wire clk,
input wire reset, input wire reset,
input [WIDTHN-1:0] numer, input wire [WIDTHN-1:0] numer,
input [WIDTHD-1:0] denom, input wire [WIDTHD-1:0] denom,
output reg [WIDTHN-1:0] quotient, output wire [WIDTHN-1:0] quotient,
output reg [WIDTHD-1:0] remainder output wire [WIDTHD-1:0] remainder
); );
`ifdef QUARTUS `ifdef QUARTUS
@@ -36,7 +36,7 @@ module VX_divide #(
quartus_div.lpm_nrepresentation = NSIGNED ? "SIGNED" : "UNSIGNED", quartus_div.lpm_nrepresentation = NSIGNED ? "SIGNED" : "UNSIGNED",
quartus_div.lpm_drepresentation = DSIGNED ? "SIGNED" : "UNSIGNED", quartus_div.lpm_drepresentation = DSIGNED ? "SIGNED" : "UNSIGNED",
quartus_div.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE", quartus_div.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE",
quartus_div.lpm_pipeline = PIPELINE; quartus_div.lpm_pipeline = PIPELINE;
`else `else

11
hw/rtl/libs/VX_encoder_onehot.v
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@@ -3,20 +3,19 @@
module VX_encoder_onehot #( module VX_encoder_onehot #(
parameter N = 6 parameter N = 6
) ( ) (
input wire [N-1:0] onehot, input wire [N-1:0] onehot,
output reg valid, output reg [`LOG2UP(N)-1:0] binary,
output reg [`LOG2UP(N)-1:0] value output reg valid
); );
integer i; integer i;
always @(*) begin always @(*) begin
valid = 1'b0; valid = 1'b0;
value = {`LOG2UP(N){1'bx}}; binary = `LOG2UP(N)'(0);
for (i = 0; i < N; i++) begin for (i = 0; i < N; i++) begin
if (onehot[i]) begin if (onehot[i]) begin
valid = 1'b1; valid = 1'b1;
value = `LOG2UP(N)'(i); binary = `LOG2UP(N)'(i);
break;
end end
end end
end end

2
hw/rtl/libs/VX_fair_arbiter.v
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@@ -1,7 +1,7 @@
`include "VX_define.vh" `include "VX_define.vh"
module VX_fair_arbiter #( module VX_fair_arbiter #(
parameter N = 0 parameter N = 1
) ( ) (
input wire clk, input wire clk,
input wire reset, input wire reset,

2
hw/rtl/libs/VX_fixed_arbiter.v
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@@ -1,7 +1,7 @@
`include "VX_define.vh" `include "VX_define.vh"
module VX_fixed_arbiter #( module VX_fixed_arbiter #(
parameter N = 0 parameter N = 1
) ( ) (
input wire clk, input wire clk,
input wire reset, input wire reset,

4
hw/rtl/libs/VX_generic_queue.v
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@@ -1,7 +1,7 @@
`include "VX_define.vh" `include "VX_define.vh"
module VX_generic_queue #( module VX_generic_queue #(
parameter DATAW, parameter DATAW = 1,
parameter SIZE = 16, parameter SIZE = 16,
parameter BUFFERED_OUTPUT = 1 parameter BUFFERED_OUTPUT = 1
) ( ) (
@@ -15,7 +15,7 @@ module VX_generic_queue #(
output wire full, output wire full,
output wire [`LOG2UP(SIZE+1)-1:0] size output wire [`LOG2UP(SIZE+1)-1:0] size
); );
`STATIC_ASSERT(`ISPOW2(SIZE), "must be 0 or power of 2!"); `STATIC_ASSERT(`ISPOW2(SIZE), "must be 0 or power of 2!")
reg [`LOG2UP(SIZE+1)-1:0] size_r; reg [`LOG2UP(SIZE+1)-1:0] size_r;
wire reading; wire reading;

2
hw/rtl/libs/VX_generic_register.v
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@@ -1,7 +1,7 @@
`include "VX_define.vh" `include "VX_define.vh"
module VX_generic_register #( module VX_generic_register #(
parameter N, parameter N = 1,
parameter PASSTHRU = 0 parameter PASSTHRU = 0
) ( ) (
input wire clk, input wire clk,

4
hw/rtl/libs/VX_indexable_queue.v
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@@ -1,8 +1,8 @@
`include "VX_define.vh" `include "VX_define.vh"
module VX_indexable_queue #( module VX_indexable_queue #(
parameter DATAW, parameter DATAW = 1,
parameter SIZE parameter SIZE = 1
) ( ) (
input wire clk, input wire clk,
input wire reset, input wire reset,

10
hw/rtl/libs/VX_matrix_arbiter.v
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@@ -1,7 +1,7 @@
`include "VX_define.vh" `include "VX_define.vh"
module VX_matrix_arbiter #( module VX_matrix_arbiter #(
parameter N = 0 parameter N = 1
) ( ) (
input wire clk, input wire clk,
input wire reset, input wire reset,
@@ -27,8 +27,8 @@ module VX_matrix_arbiter #(
genvar i, j; genvar i, j;
for (i = 0; i < N; ++i) begin for (i = 0; i < N; i++) begin
for (j = 0; j < N; ++j) begin for (j = 0; j < N; j++) begin
if (j > i) begin if (j > i) begin
assign pri[j][i] = requests[i] && state[i][j]; assign pri[j][i] = requests[i] && state[i][j];
end end
@@ -43,8 +43,8 @@ module VX_matrix_arbiter #(
assign grant_onehot[i] = requests[i] && !(| pri[i]); assign grant_onehot[i] = requests[i] && !(| pri[i]);
end end
for (i = 0; i < N; ++i) begin for (i = 0; i < N; i++) begin
for (j = i + 1; j < N; ++j) begin for (j = i + 1; j < N; j++) begin
always @(posedge clk) begin always @(posedge clk) begin
if (reset) begin if (reset) begin
state[i][j] <= 0; state[i][j] <= 0;

11
hw/rtl/libs/VX_mult.v
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@@ -7,13 +7,12 @@ module VX_mult #(
parameter SIGNED = 0, parameter SIGNED = 0,
parameter PIPELINE = 0 parameter PIPELINE = 0
) ( ) (
input clk, input wire clk,
input reset, input wire reset,
input [WIDTHA-1:0] dataa, input wire [WIDTHA-1:0] dataa,
input [WIDTHB-1:0] datab, input wire [WIDTHB-1:0] datab,
output wire [WIDTHP-1:0] result
output reg [WIDTHP-1:0] result
); );
`ifdef QUARTUS `ifdef QUARTUS

2
hw/rtl/libs/VX_priority_encoder.v
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@@ -1,7 +1,7 @@
`include "VX_define.vh" `include "VX_define.vh"
module VX_priority_encoder #( module VX_priority_encoder #(
parameter N parameter N = 1
) ( ) (
input wire [N-1:0] data_in, input wire [N-1:0] data_in,
output reg [`LOG2UP(N)-1:0] data_out, output reg [`LOG2UP(N)-1:0] data_out,

6
hw/rtl/libs/VX_rr_arbiter.v
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@@ -1,7 +1,7 @@
`include "VX_define.vh" `include "VX_define.vh"
module VX_rr_arbiter #( module VX_rr_arbiter #(
parameter N = 0 parameter N = 1
) ( ) (
input wire clk, input wire clk,
input wire reset, input wire reset,
@@ -29,9 +29,9 @@ module VX_rr_arbiter #(
integer i, j; integer i, j;
always @(*) begin always @(*) begin
for (i = 0; i < N; ++i) begin for (i = 0; i < N; i++) begin
grant_table[i] = `CLOG2(N)'(i); grant_table[i] = `CLOG2(N)'(i);
for (j = 0; j < N; ++j) begin for (j = 0; j < N; j++) begin
if (requests[(i+j) % N]) begin if (requests[(i+j) % N]) begin
grant_table[i] = `CLOG2(N)'((i+j) % N); grant_table[i] = `CLOG2(N)'((i+j) % N);
end end

2
hw/simulate/Makefile
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@@ -15,7 +15,7 @@ DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE
#DBG_FLAGS += $(DBG_PRINT_FLAGS) #DBG_FLAGS += $(DBG_PRINT_FLAGS)
DBG_FLAGS += -DDBG_CORE_REQ_INFO DBG_FLAGS += -DDBG_CORE_REQ_INFO
INCLUDE = -I../rtl/ -I../rtl/libs -I../rtl/interfaces -I../rtl/pipe_regs -I../rtl/cache -I../rtl/simulate INCLUDE = -I../rtl/ -I../rtl/libs -I../rtl/interfaces -I../rtl/cache -I../rtl/simulate
SRCS = simulator.cpp testbench.cpp SRCS = simulator.cpp testbench.cpp

2
hw/syn/quartus/core/Makefile
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@@ -49,7 +49,7 @@ smart.log: $(PROJECT_FILES)
# Project initialization # Project initialization
$(PROJECT_FILES): $(PROJECT_FILES):
quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/pipe_regs;../../../rtl/cache" quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache"
syn.chg: syn.chg:
$(STAMP) syn.chg $(STAMP) syn.chg

2
hw/syn/quartus/pipeline/Makefile
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@@ -49,7 +49,7 @@ smart.log: $(PROJECT_FILES)
# Project initialization # Project initialization
$(PROJECT_FILES): $(PROJECT_FILES):
quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/pipe_regs" quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces"
syn.chg: syn.chg:
$(STAMP) syn.chg $(STAMP) syn.chg

2
hw/syn/quartus/top/Makefile
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@@ -49,7 +49,7 @@ smart.log: $(PROJECT_FILES)
# Project initialization # Project initialization
$(PROJECT_FILES): $(PROJECT_FILES):
quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -set "NOPAE" -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/pipe_regs;../../../rtl/cache;../../../opae;../../../opae/ccip" quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -set "NOPAE" -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache;../../../opae;../../../opae/ccip"
syn.chg: syn.chg:
$(STAMP) syn.chg $(STAMP) syn.chg

2
hw/syn/quartus/vortex/Makefile
View File

@@ -49,7 +49,7 @@ smart.log: $(PROJECT_FILES)
# Project initialization # Project initialization
$(PROJECT_FILES): $(PROJECT_FILES):
quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/pipe_regs;../../../rtl/cache" quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache"
syn.chg: syn.chg:
$(STAMP) syn.chg $(STAMP) syn.chg

32
hw/syn/yosys/synth.sh Executable file
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@@ -0,0 +1,32 @@
#!/bin/bash
dir_list='../../rtl/libs ../../rtl/cache ../../rtl/interfaces ../../rtl'
inc_list=""
for dir in $dir_list; do
inc_list="$inc_list -I$dir"
done
echo "inc_list=$inc_list"
{
# read design sources
for dir in $dir_list; do
for file in $(find $dir -name '*.v' -o -name '*.sv' -type f)
do
echo "read_verilog -sv $inc_list $file"
done
done
echo "hierarchy -check -top Vortex"
# insertation of global reset
echo "add -global_input reset 1"
echo "proc -global_arst reset"
echo "synth -run coarse; opt -fine"
echo "tee -o brams.log memory_bram -rules scripts/brams.txt;;"
echo "write_verilog -noexpr -noattr synth.v"
} > synth.ys
yosys -l synth.log synth.ys

27
hw/syn/yosys/synthesis.ys
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@@ -1,27 +0,0 @@
# load design
read_verilog -sv -I../../rtl -I../../rtl/libs -I../../rtl/interfaces -I../../rtl/pipe_regs -I../../rtl/cache ../../rtl/Vortex.v
# high-level synthesis
proc; opt; fsm;; memory -nomap; opt
# substitute block rams
techmap -map map_rams.v
# map remaining memories
memory_map
# low-level synthesis
techmap; opt; flatten;; abc -lut6
techmap -map map_xl_cells.v
# add clock buffers
select -set xl_clocks t:FDRE %x:+FDRE[C] t:FDRE %d
iopadmap -inpad BUFGP O:I @xl_clocks
# add io buffers
select -set xl_nonclocks w:* t:BUFGP %x:+BUFGP[I] %d
iopadmap -outpad OBUF I:O -inpad IBUF O:I @xl_nonclocks
# write synthesis results
write_edif synth.edif