27 lines
706 B
Verilog
27 lines
706 B
Verilog
`include "VX_define.vh"
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module VX_f_d_reg (
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input wire clk,
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input wire reset,
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input wire freeze,
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VX_inst_meta_if fe_inst_meta_fd,
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VX_inst_meta_if fd_inst_meta_de
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);
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wire flush = 1'b0;
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wire stall = freeze == 1'b1;
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VX_generic_register #(
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.N(64+`NW_BITS-1+1+`NUM_THREADS)
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) f_d_reg (
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.clk (clk),
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.reset (reset),
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.stall (stall),
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.flush (flush),
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.in ({fe_inst_meta_fd.instruction, fe_inst_meta_fd.curr_PC, fe_inst_meta_fd.warp_num, fe_inst_meta_fd.valid}),
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.out ({fd_inst_meta_de.instruction, fd_inst_meta_de.curr_PC, fd_inst_meta_de.warp_num, fd_inst_meta_de.valid})
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);
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endmodule |