From bdfacf709cc47440dc1348f3234a63fc6c4adede Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Fri, 10 Jul 2020 18:56:41 -0400 Subject: [PATCH] yosys synthesis refactoring --- driver/rtlsim/Makefile | 2 +- hw/modelsim/Makefile | 4 +- hw/opae/sources.txt | 7 +- hw/rtl/{pipe_regs => }/VX_d_e_reg.v | 0 hw/rtl/{pipe_regs => }/VX_f_d_reg.v | 0 hw/rtl/{pipe_regs => }/VX_i_d_reg.v | 0 hw/rtl/VX_lsu_unit.v | 4 +- hw/rtl/Vortex.v | 116 ++++++++++++++-------------- hw/rtl/cache/VX_cache_miss_resrv.v | 2 +- hw/rtl/cache/VX_snp_forwarder.v | 2 +- hw/rtl/libs/VX_divide.v | 10 +-- hw/rtl/libs/VX_encoder_onehot.v | 11 ++- hw/rtl/libs/VX_fair_arbiter.v | 2 +- hw/rtl/libs/VX_fixed_arbiter.v | 2 +- hw/rtl/libs/VX_generic_queue.v | 4 +- hw/rtl/libs/VX_generic_register.v | 2 +- hw/rtl/libs/VX_indexable_queue.v | 4 +- hw/rtl/libs/VX_matrix_arbiter.v | 10 +-- hw/rtl/libs/VX_mult.v | 11 ++- hw/rtl/libs/VX_priority_encoder.v | 2 +- hw/rtl/libs/VX_rr_arbiter.v | 6 +- hw/simulate/Makefile | 2 +- hw/syn/quartus/core/Makefile | 2 +- hw/syn/quartus/pipeline/Makefile | 2 +- hw/syn/quartus/top/Makefile | 2 +- hw/syn/quartus/vortex/Makefile | 2 +- hw/syn/yosys/synth.sh | 32 ++++++++ hw/syn/yosys/synthesis.ys | 27 ------- 28 files changed, 136 insertions(+), 134 deletions(-) rename hw/rtl/{pipe_regs => }/VX_d_e_reg.v (100%) rename hw/rtl/{pipe_regs => }/VX_f_d_reg.v (100%) rename hw/rtl/{pipe_regs => }/VX_i_d_reg.v (100%) create mode 100755 hw/syn/yosys/synth.sh delete mode 100644 hw/syn/yosys/synthesis.ys diff --git a/driver/rtlsim/Makefile b/driver/rtlsim/Makefile index 82ab979b..d0890c4c 100644 --- a/driver/rtlsim/Makefile +++ b/driver/rtlsim/Makefile @@ -34,7 +34,7 @@ TOP = Vortex SRCS = vortex.cpp ../common/vx_utils.cpp ../../hw/simulate/simulator.cpp -RTL_INCLUDE = -I../../hw/rtl -I../../hw/rtl/libs -I../../hw/rtl/interfaces -I../../hw/rtl/pipe_regs -I../../hw/rtl/cache +RTL_INCLUDE = -I../../hw/rtl -I../../hw/rtl/libs -I../../hw/rtl/interfaces -I../../hw/rtl/cache VL_FLAGS += --language 1800-2009 --assert -Wall -Wpedantic $(CONFIGS) VL_FLAGS += -Wno-DECLFILENAME diff --git a/hw/modelsim/Makefile b/hw/modelsim/Makefile index 16cec83a..6a7b6244 100644 --- a/hw/modelsim/Makefile +++ b/hw/modelsim/Makefile @@ -69,8 +69,8 @@ SRC = \ ../rtl/cache/VX_generic_pe.v \ ../rtl/cache/cache_set.v \ ../rtl/cache/VX_cache_data_per_index.v \ -../rtl/pipe_regs/VX_d_e_reg.v \ -../rtl/pipe_regs/VX_f_d_reg.v \ +../rtl/VX_d_e_reg.v \ +../rtl/VX_f_d_reg.v \ ../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v \ ../models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.v \ ../models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0.v \ diff --git a/hw/opae/sources.txt b/hw/opae/sources.txt index e8d0480c..0b448e88 100644 --- a/hw/opae/sources.txt +++ b/hw/opae/sources.txt @@ -103,10 +103,9 @@ QI:vortex_afu.qsf ../rtl/VX_inst_multiplex.v ../rtl/VX_dcache_arb.v ../rtl/VX_mem_arb.v - -../rtl/pipe_regs/VX_f_d_reg.v -../rtl/pipe_regs/VX_i_d_reg.v -../rtl/pipe_regs/VX_d_e_reg.v +../rtl/VX_f_d_reg.v +../rtl/VX_i_d_reg.v +../rtl/VX_d_e_reg.v ccip_interface_reg.sv ccip_std_afu.sv diff --git a/hw/rtl/pipe_regs/VX_d_e_reg.v b/hw/rtl/VX_d_e_reg.v similarity index 100% rename from hw/rtl/pipe_regs/VX_d_e_reg.v rename to hw/rtl/VX_d_e_reg.v diff --git a/hw/rtl/pipe_regs/VX_f_d_reg.v b/hw/rtl/VX_f_d_reg.v similarity index 100% rename from hw/rtl/pipe_regs/VX_f_d_reg.v rename to hw/rtl/VX_f_d_reg.v diff --git a/hw/rtl/pipe_regs/VX_i_d_reg.v b/hw/rtl/VX_i_d_reg.v similarity index 100% rename from hw/rtl/pipe_regs/VX_i_d_reg.v rename to hw/rtl/VX_i_d_reg.v diff --git a/hw/rtl/VX_lsu_unit.v b/hw/rtl/VX_lsu_unit.v index f2f8af73..d1296680 100644 --- a/hw/rtl/VX_lsu_unit.v +++ b/hw/rtl/VX_lsu_unit.v @@ -59,7 +59,7 @@ module VX_lsu_unit #( wire [`NUM_THREADS-1:0][3:0] mem_req_byteen; wire [`NUM_THREADS-1:0][31:0] mem_req_data; - for (i = 0; i < `NUM_THREADS; ++i) begin + for (i = 0; i < `NUM_THREADS; i++) begin assign mem_req_addr[i] = full_address[i][31:2]; assign mem_req_offset[i] = full_address[i][1:0]; assign mem_req_byteen[i] = wmask << full_address[i][1:0]; @@ -148,7 +148,7 @@ module VX_lsu_unit #( reg [`NUM_THREADS-1:0][31:0] core_rsp_data; wire [`NUM_THREADS-1:0][31:0] rsp_data_shifted; - for (i = 0; i < `NUM_THREADS; ++i) begin + for (i = 0; i < `NUM_THREADS; i++) begin assign rsp_data_shifted[i] = dcache_rsp_if.data[i] >> {mem_rsp_offset[i], 3'b0}; always @(*) begin case (core_rsp_mem_read) diff --git a/hw/rtl/Vortex.v b/hw/rtl/Vortex.v index a606c15f..dfbf0e4a 100644 --- a/hw/rtl/Vortex.v +++ b/hw/rtl/Vortex.v @@ -139,54 +139,54 @@ module Vortex ( end else begin - wire [`NUM_CLUSTERS-1:0] per_cluster_dram_req_valid; - wire [`NUM_CLUSTERS-1:0] per_cluster_dram_req_rw; - wire [`NUM_CLUSTERS-1:0][`L2DRAM_BYTEEN_WIDTH-1:0] per_cluster_dram_req_byteen; - wire [`NUM_CLUSTERS-1:0][`L2DRAM_ADDR_WIDTH-1:0] per_cluster_dram_req_addr; - wire [`NUM_CLUSTERS-1:0][`L2DRAM_LINE_WIDTH-1:0] per_cluster_dram_req_data; - wire [`NUM_CLUSTERS-1:0][`L2DRAM_TAG_WIDTH-1:0] per_cluster_dram_req_tag; - wire l3_core_req_ready; + wire per_cluster_dram_req_valid [`NUM_CLUSTERS-1:0]; + wire per_cluster_dram_req_rw [`NUM_CLUSTERS-1:0]; + wire [`L2DRAM_BYTEEN_WIDTH-1:0] per_cluster_dram_req_byteen [`NUM_CLUSTERS-1:0]; + wire [`L2DRAM_ADDR_WIDTH-1:0] per_cluster_dram_req_addr [`NUM_CLUSTERS-1:0]; + wire [`L2DRAM_LINE_WIDTH-1:0] per_cluster_dram_req_data [`NUM_CLUSTERS-1:0]; + wire [`L2DRAM_TAG_WIDTH-1:0] per_cluster_dram_req_tag [`NUM_CLUSTERS-1:0]; + wire l3_core_req_ready; - wire [`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_valid; - wire [`NUM_CLUSTERS-1:0][`L2DRAM_LINE_WIDTH-1:0] per_cluster_dram_rsp_data; - wire [`NUM_CLUSTERS-1:0][`L2DRAM_TAG_WIDTH-1:0] per_cluster_dram_rsp_tag; - wire [`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_ready; + wire per_cluster_dram_rsp_valid [`NUM_CLUSTERS-1:0]; + wire [`L2DRAM_LINE_WIDTH-1:0] per_cluster_dram_rsp_data [`NUM_CLUSTERS-1:0]; + wire [`L2DRAM_TAG_WIDTH-1:0] per_cluster_dram_rsp_tag [`NUM_CLUSTERS-1:0]; + wire per_cluster_dram_rsp_ready [`NUM_CLUSTERS-1:0]; - wire [`NUM_CLUSTERS-1:0] per_cluster_snp_req_valid; - wire [`NUM_CLUSTERS-1:0][`L2DRAM_ADDR_WIDTH-1:0] per_cluster_snp_req_addr; - wire [`NUM_CLUSTERS-1:0] per_cluster_snp_req_invalidate; - wire [`NUM_CLUSTERS-1:0][`L2SNP_TAG_WIDTH-1:0] per_cluster_snp_req_tag; - wire [`NUM_CLUSTERS-1:0] per_cluster_snp_req_ready; + wire per_cluster_snp_req_valid [`NUM_CLUSTERS-1:0]; + wire [`L2DRAM_ADDR_WIDTH-1:0] per_cluster_snp_req_addr [`NUM_CLUSTERS-1:0]; + wire per_cluster_snp_req_invalidate [`NUM_CLUSTERS-1:0]; + wire [`L2SNP_TAG_WIDTH-1:0] per_cluster_snp_req_tag [`NUM_CLUSTERS-1:0]; + wire per_cluster_snp_req_ready [`NUM_CLUSTERS-1:0]; - wire [`NUM_CLUSTERS-1:0] per_cluster_snp_rsp_valid; - wire [`NUM_CLUSTERS-1:0][`L2SNP_TAG_WIDTH-1:0] per_cluster_snp_rsp_tag; - wire [`NUM_CLUSTERS-1:0] per_cluster_snp_rsp_ready; + wire per_cluster_snp_rsp_valid [`NUM_CLUSTERS-1:0]; + wire [`L2SNP_TAG_WIDTH-1:0] per_cluster_snp_rsp_tag [`NUM_CLUSTERS-1:0]; + wire per_cluster_snp_rsp_ready [`NUM_CLUSTERS-1:0]; - wire [`NUM_CLUSTERS-1:0] per_cluster_io_req_valid; - wire [`NUM_CLUSTERS-1:0] per_cluster_io_req_rw; - wire [`NUM_CLUSTERS-1:0][3:0] per_cluster_io_req_byteen; - wire [`NUM_CLUSTERS-1:0][29:0] per_cluster_io_req_addr; - wire [`NUM_CLUSTERS-1:0][31:0] per_cluster_io_req_data; - wire [`NUM_CLUSTERS-1:0][`L2CORE_TAG_WIDTH-1:0] per_cluster_io_req_tag; - wire [`NUM_CLUSTERS-1:0] per_cluster_io_req_ready; + wire per_cluster_io_req_valid [`NUM_CLUSTERS-1:0]; + wire per_cluster_io_req_rw [`NUM_CLUSTERS-1:0]; + wire [3:0] per_cluster_io_req_byteen [`NUM_CLUSTERS-1:0]; + wire [29:0] per_cluster_io_req_addr [`NUM_CLUSTERS-1:0]; + wire [31:0] per_cluster_io_req_data [`NUM_CLUSTERS-1:0]; + wire [`L2CORE_TAG_WIDTH-1:0] per_cluster_io_req_tag [`NUM_CLUSTERS-1:0]; + wire per_cluster_io_req_ready [`NUM_CLUSTERS-1:0]; - wire [`NUM_CLUSTERS-1:0] per_cluster_io_rsp_valid; - wire [`NUM_CLUSTERS-1:0][`L2CORE_TAG_WIDTH-1:0] per_cluster_io_rsp_tag; - wire [`NUM_CLUSTERS-1:0][31:0] per_cluster_io_rsp_data; - wire [`NUM_CLUSTERS-1:0] per_cluster_io_rsp_ready; + wire per_cluster_io_rsp_valid [`NUM_CLUSTERS-1:0]; + wire [`L2CORE_TAG_WIDTH-1:0] per_cluster_io_rsp_tag [`NUM_CLUSTERS-1:0]; + wire [31:0] per_cluster_io_rsp_data [`NUM_CLUSTERS-1:0]; + wire per_cluster_io_rsp_ready [`NUM_CLUSTERS-1:0]; - wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_req_valid; - wire [`NUM_CLUSTERS-1:0][11:0] per_cluster_csr_io_req_addr; - wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_req_rw; - wire [`NUM_CLUSTERS-1:0][31:0] per_cluster_csr_io_req_data; - wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_req_ready; + wire per_cluster_csr_io_req_valid [`NUM_CLUSTERS-1:0]; + wire [11:0] per_cluster_csr_io_req_addr [`NUM_CLUSTERS-1:0]; + wire per_cluster_csr_io_req_rw [`NUM_CLUSTERS-1:0]; + wire [31:0] per_cluster_csr_io_req_data [`NUM_CLUSTERS-1:0]; + wire per_cluster_csr_io_req_ready [`NUM_CLUSTERS-1:0]; - wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_rsp_valid; - wire [`NUM_CLUSTERS-1:0][31:0] per_cluster_csr_io_rsp_data; - wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_rsp_ready; + wire per_cluster_csr_io_rsp_valid [`NUM_CLUSTERS-1:0]; + wire [31:0] per_cluster_csr_io_rsp_data [`NUM_CLUSTERS-1:0]; + wire per_cluster_csr_io_rsp_ready [`NUM_CLUSTERS-1:0]; - wire [`NUM_CLUSTERS-1:0] per_cluster_busy; - wire [`NUM_CLUSTERS-1:0] per_cluster_ebreak; + wire per_cluster_busy [`NUM_CLUSTERS-1:0]; + wire per_cluster_ebreak [`NUM_CLUSTERS-1:0]; wire [`CLOG2(`NUM_CLUSTERS)-1:0] csr_io_request_id = `CLOG2(`NUM_CLUSTERS)'(csr_io_req_coreid >> `CLOG2(`NUM_CLUSTERS)); wire [`NC_BITS-1:0] per_cluster_csr_io_req_coreid = `NC_BITS'(csr_io_req_coreid); @@ -336,27 +336,27 @@ module Vortex ( // L3 Cache /////////////////////////////////////////////////////////// - wire [`L3NUM_REQUESTS-1:0] l3_core_req_valid; - wire [`L3NUM_REQUESTS-1:0] l3_core_req_rw; - wire [`L3NUM_REQUESTS-1:0][`L2DRAM_BYTEEN_WIDTH-1:0] l3_core_req_byteen; - wire [`L3NUM_REQUESTS-1:0][`L2DRAM_ADDR_WIDTH-1:0] l3_core_req_addr; - wire [`L3NUM_REQUESTS-1:0][`L2DRAM_LINE_WIDTH-1:0] l3_core_req_data; - wire [`L3NUM_REQUESTS-1:0][`L2DRAM_TAG_WIDTH-1:0] l3_core_req_tag; + wire l3_core_req_valid [`L3NUM_REQUESTS-1:0]; + wire l3_core_req_rw [`L3NUM_REQUESTS-1:0]; + wire [`L2DRAM_BYTEEN_WIDTH-1:0] l3_core_req_byteen [`L3NUM_REQUESTS-1:0]; + wire [`L2DRAM_ADDR_WIDTH-1:0] l3_core_req_addr [`L3NUM_REQUESTS-1:0]; + wire [`L2DRAM_LINE_WIDTH-1:0] l3_core_req_data [`L3NUM_REQUESTS-1:0]; + wire [`L2DRAM_TAG_WIDTH-1:0] l3_core_req_tag [`L3NUM_REQUESTS-1:0]; - wire [`L3NUM_REQUESTS-1:0] l3_core_rsp_valid; - wire [`L3NUM_REQUESTS-1:0][`L2DRAM_LINE_WIDTH-1:0] l3_core_rsp_data; - wire [`L3NUM_REQUESTS-1:0][`L2DRAM_TAG_WIDTH-1:0] l3_core_rsp_tag; - wire l3_core_rsp_ready; + wire l3_core_rsp_valid [`L3NUM_REQUESTS-1:0]; + wire [`L2DRAM_LINE_WIDTH-1:0] l3_core_rsp_data [`L3NUM_REQUESTS-1:0]; + wire [`L2DRAM_TAG_WIDTH-1:0] l3_core_rsp_tag [`L3NUM_REQUESTS-1:0]; + wire l3_core_rsp_ready; - wire [`NUM_CLUSTERS-1:0] l3_snp_fwdout_valid; - wire [`NUM_CLUSTERS-1:0][`L2DRAM_ADDR_WIDTH-1:0] l3_snp_fwdout_addr; - wire [`NUM_CLUSTERS-1:0] l3_snp_fwdout_invalidate; - wire [`NUM_CLUSTERS-1:0][`L2SNP_TAG_WIDTH-1:0] l3_snp_fwdout_tag; - wire [`NUM_CLUSTERS-1:0] l3_snp_fwdout_ready; + wire l3_snp_fwdout_valid [`NUM_CLUSTERS-1:0]; + wire [`L2DRAM_ADDR_WIDTH-1:0] l3_snp_fwdout_addr [`NUM_CLUSTERS-1:0]; + wire l3_snp_fwdout_invalidate [`NUM_CLUSTERS-1:0]; + wire [`L2SNP_TAG_WIDTH-1:0] l3_snp_fwdout_tag [`NUM_CLUSTERS-1:0]; + wire l3_snp_fwdout_ready [`NUM_CLUSTERS-1:0]; - wire [`NUM_CLUSTERS-1:0] l3_snp_fwdin_valid; - wire [`NUM_CLUSTERS-1:0][`L2SNP_TAG_WIDTH-1:0] l3_snp_fwdin_tag; - wire [`NUM_CLUSTERS-1:0] l3_snp_fwdin_ready; + wire l3_snp_fwdin_valid [`NUM_CLUSTERS-1:0]; + wire [`L2SNP_TAG_WIDTH-1:0] l3_snp_fwdin_tag [`NUM_CLUSTERS-1:0]; + wire l3_snp_fwdin_ready [`NUM_CLUSTERS-1:0]; for (i = 0; i < `L3NUM_REQUESTS; i++) begin // Core Request diff --git a/hw/rtl/cache/VX_cache_miss_resrv.v b/hw/rtl/cache/VX_cache_miss_resrv.v index d4e6d5ee..c851629c 100644 --- a/hw/rtl/cache/VX_cache_miss_resrv.v +++ b/hw/rtl/cache/VX_cache_miss_resrv.v @@ -66,7 +66,7 @@ module VX_cache_miss_resrv #( reg [`LOG2UP(MRVQ_SIZE+1)-1:0] size; - `STATIC_ASSERT(MRVQ_SIZE > 5, "invalid size"); + `STATIC_ASSERT(MRVQ_SIZE > 5, "invalid size") assign miss_resrv_full = (size == $bits(size)'(MRVQ_SIZE)); assign miss_resrv_stop = (size > $bits(size)'(MRVQ_SIZE-5)); // need to add 5 cycles to prevent pipeline lock diff --git a/hw/rtl/cache/VX_snp_forwarder.v b/hw/rtl/cache/VX_snp_forwarder.v index 0536d393..f54b6eba 100644 --- a/hw/rtl/cache/VX_snp_forwarder.v +++ b/hw/rtl/cache/VX_snp_forwarder.v @@ -37,7 +37,7 @@ module VX_snp_forwarder #( input wire [NUM_REQUESTS-1:0][`LOG2UP(SNRQ_SIZE)-1:0] snp_fwdin_tag, output wire [NUM_REQUESTS-1:0] snp_fwdin_ready ); - `STATIC_ASSERT(NUM_REQUESTS > 1, "invalid value"); + `STATIC_ASSERT(NUM_REQUESTS > 1, "invalid value") reg [`REQS_BITS:0] pending_cntrs [SNRQ_SIZE-1:0]; diff --git a/hw/rtl/libs/VX_divide.v b/hw/rtl/libs/VX_divide.v index f32aeb13..510abf26 100644 --- a/hw/rtl/libs/VX_divide.v +++ b/hw/rtl/libs/VX_divide.v @@ -10,11 +10,11 @@ module VX_divide #( input wire clk, input wire reset, - input [WIDTHN-1:0] numer, - input [WIDTHD-1:0] denom, + input wire [WIDTHN-1:0] numer, + input wire [WIDTHD-1:0] denom, - output reg [WIDTHN-1:0] quotient, - output reg [WIDTHD-1:0] remainder + output wire [WIDTHN-1:0] quotient, + output wire [WIDTHD-1:0] remainder ); `ifdef QUARTUS @@ -36,7 +36,7 @@ module VX_divide #( quartus_div.lpm_nrepresentation = NSIGNED ? "SIGNED" : "UNSIGNED", quartus_div.lpm_drepresentation = DSIGNED ? "SIGNED" : "UNSIGNED", quartus_div.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE", - quartus_div.lpm_pipeline = PIPELINE; + quartus_div.lpm_pipeline = PIPELINE; `else diff --git a/hw/rtl/libs/VX_encoder_onehot.v b/hw/rtl/libs/VX_encoder_onehot.v index e5e06ff0..a4e0e72e 100644 --- a/hw/rtl/libs/VX_encoder_onehot.v +++ b/hw/rtl/libs/VX_encoder_onehot.v @@ -3,20 +3,19 @@ module VX_encoder_onehot #( parameter N = 6 ) ( - input wire [N-1:0] onehot, - output reg valid, - output reg [`LOG2UP(N)-1:0] value + input wire [N-1:0] onehot, + output reg [`LOG2UP(N)-1:0] binary, + output reg valid ); integer i; always @(*) begin valid = 1'b0; - value = {`LOG2UP(N){1'bx}}; + binary = `LOG2UP(N)'(0); for (i = 0; i < N; i++) begin if (onehot[i]) begin valid = 1'b1; - value = `LOG2UP(N)'(i); - break; + binary = `LOG2UP(N)'(i); end end end diff --git a/hw/rtl/libs/VX_fair_arbiter.v b/hw/rtl/libs/VX_fair_arbiter.v index 5ac5749e..9ffc1ecd 100644 --- a/hw/rtl/libs/VX_fair_arbiter.v +++ b/hw/rtl/libs/VX_fair_arbiter.v @@ -1,7 +1,7 @@ `include "VX_define.vh" module VX_fair_arbiter #( - parameter N = 0 + parameter N = 1 ) ( input wire clk, input wire reset, diff --git a/hw/rtl/libs/VX_fixed_arbiter.v b/hw/rtl/libs/VX_fixed_arbiter.v index 0ce69146..7f6fbfa3 100644 --- a/hw/rtl/libs/VX_fixed_arbiter.v +++ b/hw/rtl/libs/VX_fixed_arbiter.v @@ -1,7 +1,7 @@ `include "VX_define.vh" module VX_fixed_arbiter #( - parameter N = 0 + parameter N = 1 ) ( input wire clk, input wire reset, diff --git a/hw/rtl/libs/VX_generic_queue.v b/hw/rtl/libs/VX_generic_queue.v index 52e12831..a666948b 100644 --- a/hw/rtl/libs/VX_generic_queue.v +++ b/hw/rtl/libs/VX_generic_queue.v @@ -1,7 +1,7 @@ `include "VX_define.vh" module VX_generic_queue #( - parameter DATAW, + parameter DATAW = 1, parameter SIZE = 16, parameter BUFFERED_OUTPUT = 1 ) ( @@ -15,7 +15,7 @@ module VX_generic_queue #( output wire full, output wire [`LOG2UP(SIZE+1)-1:0] size ); - `STATIC_ASSERT(`ISPOW2(SIZE), "must be 0 or power of 2!"); + `STATIC_ASSERT(`ISPOW2(SIZE), "must be 0 or power of 2!") reg [`LOG2UP(SIZE+1)-1:0] size_r; wire reading; diff --git a/hw/rtl/libs/VX_generic_register.v b/hw/rtl/libs/VX_generic_register.v index 869efdd4..7234b0a2 100644 --- a/hw/rtl/libs/VX_generic_register.v +++ b/hw/rtl/libs/VX_generic_register.v @@ -1,7 +1,7 @@ `include "VX_define.vh" module VX_generic_register #( - parameter N, + parameter N = 1, parameter PASSTHRU = 0 ) ( input wire clk, diff --git a/hw/rtl/libs/VX_indexable_queue.v b/hw/rtl/libs/VX_indexable_queue.v index b6749e81..886b05f6 100644 --- a/hw/rtl/libs/VX_indexable_queue.v +++ b/hw/rtl/libs/VX_indexable_queue.v @@ -1,8 +1,8 @@ `include "VX_define.vh" module VX_indexable_queue #( - parameter DATAW, - parameter SIZE + parameter DATAW = 1, + parameter SIZE = 1 ) ( input wire clk, input wire reset, diff --git a/hw/rtl/libs/VX_matrix_arbiter.v b/hw/rtl/libs/VX_matrix_arbiter.v index 1d578166..8c467974 100644 --- a/hw/rtl/libs/VX_matrix_arbiter.v +++ b/hw/rtl/libs/VX_matrix_arbiter.v @@ -1,7 +1,7 @@ `include "VX_define.vh" module VX_matrix_arbiter #( - parameter N = 0 + parameter N = 1 ) ( input wire clk, input wire reset, @@ -27,8 +27,8 @@ module VX_matrix_arbiter #( genvar i, j; - for (i = 0; i < N; ++i) begin - for (j = 0; j < N; ++j) begin + for (i = 0; i < N; i++) begin + for (j = 0; j < N; j++) begin if (j > i) begin assign pri[j][i] = requests[i] && state[i][j]; end @@ -43,8 +43,8 @@ module VX_matrix_arbiter #( assign grant_onehot[i] = requests[i] && !(| pri[i]); end - for (i = 0; i < N; ++i) begin - for (j = i + 1; j < N; ++j) begin + for (i = 0; i < N; i++) begin + for (j = i + 1; j < N; j++) begin always @(posedge clk) begin if (reset) begin state[i][j] <= 0; diff --git a/hw/rtl/libs/VX_mult.v b/hw/rtl/libs/VX_mult.v index 16d47d6d..1dd77aea 100644 --- a/hw/rtl/libs/VX_mult.v +++ b/hw/rtl/libs/VX_mult.v @@ -7,13 +7,12 @@ module VX_mult #( parameter SIGNED = 0, parameter PIPELINE = 0 ) ( - input clk, - input reset, + input wire clk, + input wire reset, - input [WIDTHA-1:0] dataa, - input [WIDTHB-1:0] datab, - - output reg [WIDTHP-1:0] result + input wire [WIDTHA-1:0] dataa, + input wire [WIDTHB-1:0] datab, + output wire [WIDTHP-1:0] result ); `ifdef QUARTUS diff --git a/hw/rtl/libs/VX_priority_encoder.v b/hw/rtl/libs/VX_priority_encoder.v index e98a17d6..24c91724 100644 --- a/hw/rtl/libs/VX_priority_encoder.v +++ b/hw/rtl/libs/VX_priority_encoder.v @@ -1,7 +1,7 @@ `include "VX_define.vh" module VX_priority_encoder #( - parameter N + parameter N = 1 ) ( input wire [N-1:0] data_in, output reg [`LOG2UP(N)-1:0] data_out, diff --git a/hw/rtl/libs/VX_rr_arbiter.v b/hw/rtl/libs/VX_rr_arbiter.v index d093cd60..fb19e108 100644 --- a/hw/rtl/libs/VX_rr_arbiter.v +++ b/hw/rtl/libs/VX_rr_arbiter.v @@ -1,7 +1,7 @@ `include "VX_define.vh" module VX_rr_arbiter #( - parameter N = 0 + parameter N = 1 ) ( input wire clk, input wire reset, @@ -29,9 +29,9 @@ module VX_rr_arbiter #( integer i, j; always @(*) begin - for (i = 0; i < N; ++i) begin + for (i = 0; i < N; i++) begin grant_table[i] = `CLOG2(N)'(i); - for (j = 0; j < N; ++j) begin + for (j = 0; j < N; j++) begin if (requests[(i+j) % N]) begin grant_table[i] = `CLOG2(N)'((i+j) % N); end diff --git a/hw/simulate/Makefile b/hw/simulate/Makefile index 21814760..7b665714 100644 --- a/hw/simulate/Makefile +++ b/hw/simulate/Makefile @@ -15,7 +15,7 @@ DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE #DBG_FLAGS += $(DBG_PRINT_FLAGS) DBG_FLAGS += -DDBG_CORE_REQ_INFO -INCLUDE = -I../rtl/ -I../rtl/libs -I../rtl/interfaces -I../rtl/pipe_regs -I../rtl/cache -I../rtl/simulate +INCLUDE = -I../rtl/ -I../rtl/libs -I../rtl/interfaces -I../rtl/cache -I../rtl/simulate SRCS = simulator.cpp testbench.cpp diff --git a/hw/syn/quartus/core/Makefile b/hw/syn/quartus/core/Makefile index 69ab23ab..0968b478 100644 --- a/hw/syn/quartus/core/Makefile +++ b/hw/syn/quartus/core/Makefile @@ -49,7 +49,7 @@ smart.log: $(PROJECT_FILES) # Project initialization $(PROJECT_FILES): - quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/pipe_regs;../../../rtl/cache" + quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache" syn.chg: $(STAMP) syn.chg diff --git a/hw/syn/quartus/pipeline/Makefile b/hw/syn/quartus/pipeline/Makefile index b2ed2d5e..49232fe8 100644 --- a/hw/syn/quartus/pipeline/Makefile +++ b/hw/syn/quartus/pipeline/Makefile @@ -49,7 +49,7 @@ smart.log: $(PROJECT_FILES) # Project initialization $(PROJECT_FILES): - quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/pipe_regs" + quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces" syn.chg: $(STAMP) syn.chg diff --git a/hw/syn/quartus/top/Makefile b/hw/syn/quartus/top/Makefile index dbb4844f..c6219230 100644 --- a/hw/syn/quartus/top/Makefile +++ b/hw/syn/quartus/top/Makefile @@ -49,7 +49,7 @@ smart.log: $(PROJECT_FILES) # Project initialization $(PROJECT_FILES): - quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -set "NOPAE" -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/pipe_regs;../../../rtl/cache;../../../opae;../../../opae/ccip" + quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -set "NOPAE" -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache;../../../opae;../../../opae/ccip" syn.chg: $(STAMP) syn.chg diff --git a/hw/syn/quartus/vortex/Makefile b/hw/syn/quartus/vortex/Makefile index 4e9badb1..f8db7cc8 100644 --- a/hw/syn/quartus/vortex/Makefile +++ b/hw/syn/quartus/vortex/Makefile @@ -49,7 +49,7 @@ smart.log: $(PROJECT_FILES) # Project initialization $(PROJECT_FILES): - quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/pipe_regs;../../../rtl/cache" + quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache" syn.chg: $(STAMP) syn.chg diff --git a/hw/syn/yosys/synth.sh b/hw/syn/yosys/synth.sh new file mode 100755 index 00000000..621866f1 --- /dev/null +++ b/hw/syn/yosys/synth.sh @@ -0,0 +1,32 @@ +#!/bin/bash + +dir_list='../../rtl/libs ../../rtl/cache ../../rtl/interfaces ../../rtl' + +inc_list="" +for dir in $dir_list; do + inc_list="$inc_list -I$dir" +done + +echo "inc_list=$inc_list" + +{ + # read design sources + for dir in $dir_list; do + for file in $(find $dir -name '*.v' -o -name '*.sv' -type f) + do + echo "read_verilog -sv $inc_list $file" + done + done + + echo "hierarchy -check -top Vortex" + + # insertation of global reset + echo "add -global_input reset 1" + echo "proc -global_arst reset" + + echo "synth -run coarse; opt -fine" + echo "tee -o brams.log memory_bram -rules scripts/brams.txt;;" + echo "write_verilog -noexpr -noattr synth.v" +} > synth.ys + +yosys -l synth.log synth.ys \ No newline at end of file diff --git a/hw/syn/yosys/synthesis.ys b/hw/syn/yosys/synthesis.ys deleted file mode 100644 index fd208160..00000000 --- a/hw/syn/yosys/synthesis.ys +++ /dev/null @@ -1,27 +0,0 @@ -# load design -read_verilog -sv -I../../rtl -I../../rtl/libs -I../../rtl/interfaces -I../../rtl/pipe_regs -I../../rtl/cache ../../rtl/Vortex.v - -# high-level synthesis -proc; opt; fsm;; memory -nomap; opt - -# substitute block rams -techmap -map map_rams.v - -# map remaining memories -memory_map - -# low-level synthesis -techmap; opt; flatten;; abc -lut6 -techmap -map map_xl_cells.v - -# add clock buffers -select -set xl_clocks t:FDRE %x:+FDRE[C] t:FDRE %d -iopadmap -inpad BUFGP O:I @xl_clocks - -# add io buffers -select -set xl_nonclocks w:* t:BUFGP %x:+BUFGP[I] %d -iopadmap -outpad OBUF I:O -inpad IBUF O:I @xl_nonclocks - -# write synthesis results -write_edif synth.edif -