feat: support 4-lane pre-WU Blackwell RTL

hw/rtl/VX_core_wrapper.sv

@@ -82,7 +82,7 @@ module Vortex import VX_gpu_pkg::*; #(
     output [2:0]   tc_a_bits_write,
     output [95:0]  tc_a_bits_address,
     output [3 * TC_TAG_WIDTH - 1:0] tc_a_bits_tag,
-    output [3 * 32 - 1:0] tc_a_bits_mask,
+    output [3 * (TC_DATA_WIDTH / 8) - 1:0] tc_a_bits_mask,
     output [3 * TC_DATA_WIDTH - 1:0] tc_a_bits_data,
     output [2:0]   tc_d_ready,
     input  [2:0]   tc_d_valid,

hw/rtl/VX_platform.vh

@@ -33,9 +33,9 @@
 
 `ifdef SYNTHESIS
 `define NUM_BARRIERS 8
-`define NUM_CORES 4
-`define NUM_THREADS 8
-`define NUM_WARPS 8
+`define NUM_CORES 1
+`define NUM_THREADS 4
+`define NUM_WARPS 4
 
 `define FPU_FPNEW
 // `define FIRESIM