From 9560f9cab6294c55a4127404645715dec40d3ff5 Mon Sep 17 00:00:00 2001 From: Zhongdi LUO Date: Mon, 13 Jul 2026 06:29:04 +0000 Subject: [PATCH] feat: support 4-lane pre-WU Blackwell RTL --- hw/rtl/VX_core_wrapper.sv | 2 +- hw/rtl/VX_platform.vh | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/rtl/VX_core_wrapper.sv b/hw/rtl/VX_core_wrapper.sv index b6bd737d..b23f8c3f 100644 --- a/hw/rtl/VX_core_wrapper.sv +++ b/hw/rtl/VX_core_wrapper.sv @@ -82,7 +82,7 @@ module Vortex import VX_gpu_pkg::*; #( output [2:0] tc_a_bits_write, output [95:0] tc_a_bits_address, output [3 * TC_TAG_WIDTH - 1:0] tc_a_bits_tag, - output [3 * 32 - 1:0] tc_a_bits_mask, + output [3 * (TC_DATA_WIDTH / 8) - 1:0] tc_a_bits_mask, output [3 * TC_DATA_WIDTH - 1:0] tc_a_bits_data, output [2:0] tc_d_ready, input [2:0] tc_d_valid, diff --git a/hw/rtl/VX_platform.vh b/hw/rtl/VX_platform.vh index bf544995..d07f7d6e 100644 --- a/hw/rtl/VX_platform.vh +++ b/hw/rtl/VX_platform.vh @@ -33,9 +33,9 @@ `ifdef SYNTHESIS `define NUM_BARRIERS 8 -`define NUM_CORES 4 -`define NUM_THREADS 8 -`define NUM_WARPS 8 +`define NUM_CORES 1 +`define NUM_THREADS 4 +`define NUM_WARPS 4 `define FPU_FPNEW // `define FIRESIM