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pipeline refactoring - fmax >= 222 mhz

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This commit is contained in:
Blaise Tine
2020-08-14 21:50:14 -07:00
parent 71a46d04b9
commit 6c12391338
107 changed files with 1392 additions and 1239 deletions
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14
hw/rtl/interfaces/VX_alu_req_if.v
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@@ -7,18 +7,22 @@ interface VX_alu_req_if ();
wire valid;
wire [`ISTAG_BITS-1:0] issue_tag;
`DEBUG_BEGIN
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] thread_mask;
wire [`NW_BITS-1:0] warp_num;
`DEBUG_END
wire [31:0] curr_PC;
wire [`ALU_BITS-1:0] alu_op;
wire [`ALU_BITS-1:0] op;
wire rs1_is_PC;
wire rs2_is_imm;
wire [31:0] imm;
wire [`NUM_THREADS-1:0][31:0] rs1_data;
wire [`NUM_THREADS-1:0][31:0] rs2_data;
wire [31:0] offset;
wire [31:0] next_PC;
wire ready;
endinterface

2
hw/rtl/interfaces/VX_branch_ctl_if.v
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@@ -6,7 +6,7 @@
interface VX_branch_ctl_if ();
wire valid;
wire [`NW_BITS-1:0] warp_num;
wire [`NW_BITS-1:0] wid;
wire taken;
wire [31:0] dest;

29
hw/rtl/interfaces/VX_bru_req_if.v Normal file
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@@ -0,0 +1,29 @@
`ifndef VX_BRANCH_REQ_IF
`define VX_BRANCH_REQ_IF
`include "VX_define.vh"
interface VX_bru_req_if ();
wire valid;
wire [`ISTAG_BITS-1:0] issue_tag;
wire [`NW_BITS-1:0] wid;
`DEBUG_BEGIN
wire [`NUM_THREADS-1:0] thread_mask;
`DEBUG_END
wire [31:0] curr_PC;
wire [`BRU_BITS-1:0] op;
wire rs1_is_PC;
wire [31:0] rs1_data;
wire [31:0] rs2_data;
wire [31:0] offset;
wire ready;
endinterface
`endif

2
hw/rtl/interfaces/VX_cmt_to_csr_if.v
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@@ -7,7 +7,7 @@ interface VX_cmt_to_csr_if ();
wire valid;
wire [`NW_BITS-1:0] warp_num;
wire [`NW_BITS-1:0] wid;
wire [`NE_BITS:0] num_commits;

3
hw/rtl/interfaces/VX_cmt_to_issue_if.v
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@@ -6,6 +6,7 @@
interface VX_cmt_to_issue_if ();
wire alu_valid;
wire bru_valid;
wire lsu_valid;
wire csr_valid;
wire mul_valid;
@@ -13,6 +14,7 @@ interface VX_cmt_to_issue_if ();
wire gpu_valid;
wire [`ISTAG_BITS-1:0] alu_tag;
wire [`ISTAG_BITS-1:0] bru_tag;
wire [`ISTAG_BITS-1:0] lsu_tag;
wire [`ISTAG_BITS-1:0] csr_tag;
wire [`ISTAG_BITS-1:0] mul_tag;
@@ -21,6 +23,7 @@ interface VX_cmt_to_issue_if ();
`IGNORE_WARNINGS_BEGIN
issue_data_t alu_data;
issue_data_t bru_data;
issue_data_t lsu_data;
issue_data_t csr_data;
issue_data_t mul_data;

4
hw/rtl/interfaces/VX_csr_req_if.v
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@@ -7,13 +7,13 @@ interface VX_csr_req_if ();
wire valid;
wire [`ISTAG_BITS-1:0] issue_tag;
wire [`NW_BITS-1:0] wid;
`DEBUG_BEGIN
wire [`NUM_THREADS-1:0] thread_mask;
`DEBUG_END
wire [`NW_BITS-1:0] warp_num;
wire [31:0] curr_PC;
wire [`CSR_BITS-1:0] csr_op;
wire [`CSR_BITS-1:0] op;
wire [`CSR_ADDR_BITS-1:0] csr_addr;
wire [31:0] csr_mask;

15
hw/rtl/interfaces/VX_csr_rsp_if.v Normal file
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@@ -0,0 +1,15 @@
`ifndef VX_CSR_RSP_IF
`define VX_CSR_RSP_IF
`include "VX_define.vh"
interface VX_csr_rsp_if ();
wire valid;
wire [`ISTAG_BITS-1:0] issue_tag;
wire [`NUM_THREADS-1:0][31:0] data;
wire ready;
endinterface
`endif

2
hw/rtl/interfaces/VX_csr_to_fpu_if.v
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@@ -9,7 +9,7 @@
interface VX_csr_to_fpu_if ();
wire [`NW_BITS-1:0] warp_num;
wire [`NW_BITS-1:0] wid;
wire [`FRM_BITS-1:0] frm;
endinterface

3
hw/rtl/interfaces/VX_decode_if.v
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@@ -6,10 +6,9 @@
interface VX_decode_if ();
wire valid;
wire [`NW_BITS-1:0] warp_num;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] thread_mask;
wire [31:0] curr_PC;
wire [31:0] next_PC;
wire [`EX_BITS-1:0] ex_type;
wire [`OP_BITS-1:0] ex_op;

7
hw/rtl/interfaces/VX_exu_to_cmt_if.v
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@@ -5,10 +5,9 @@
interface VX_exu_to_cmt_if ();
wire valid;
wire [`ISTAG_BITS-1:0] issue_tag;
wire [`NUM_THREADS-1:0][31:0] data;
wire ready;
wire valid;
wire [`ISTAG_BITS-1:0] issue_tag;
wire [`NUM_THREADS-1:0][31:0] data;
endinterface

6
hw/rtl/interfaces/VX_fpu_req_if.v
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@@ -11,13 +11,13 @@ interface VX_fpu_req_if ();
wire valid;
wire [`ISTAG_BITS-1:0] issue_tag;
wire [`NW_BITS-1:0] wid;
`DEBUG_BEGIN
wire [`NUM_THREADS-1:0] thread_mask;
`DEBUG_END
wire [`NW_BITS-1:0] warp_num;
wire [31:0] curr_PC;
`DEBUG_END
wire [`FPU_BITS-1:0] fpu_op;
wire [`FPU_BITS-1:0] op;
wire [`FRM_BITS-1:0] frm;
wire [`NUM_THREADS-1:0][31:0] rs1_data;

1
hw/rtl/interfaces/VX_fpu_to_cmt_if.v
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@@ -10,7 +10,6 @@ interface VX_fpu_to_cmt_if ();
wire [`NUM_THREADS-1:0][31:0] data;
wire has_fflags;
fflags_t [`NUM_THREADS-1:0] fflags;
wire ready;
endinterface

2
hw/rtl/interfaces/VX_fpu_to_csr_if.v
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@@ -11,7 +11,7 @@ interface VX_fpu_to_csr_if ();
wire valid;
wire [`NW_BITS-1:0] warp_num;
wire [`NW_BITS-1:0] wid;
wire fflags_NV;
wire fflags_DZ;

2
hw/rtl/interfaces/VX_gpr_read_if.v
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@@ -7,7 +7,7 @@ interface VX_gpr_read_if ();
wire valid;
wire [`NW_BITS-1:0] warp_num;
wire [`NW_BITS-1:0] wid;
wire [`NR_BITS-1:0] rs1;
wire [`NR_BITS-1:0] rs2;

10
hw/rtl/interfaces/VX_gpu_req_if.v
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@@ -6,17 +6,15 @@
interface VX_gpu_req_if();
wire valid;
wire [`ISTAG_BITS-1:0] issue_tag;
wire [`ISTAG_BITS-1:0] issue_tag;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] thread_mask;
wire [`NW_BITS-1:0] warp_num;
`DEBUG_BEGIN
wire [31:0] curr_PC;
`DEBUG_END
wire [`GPU_BITS-1:0] gpu_op;
wire [`GPU_BITS-1:0] op;
wire [`NUM_THREADS-1:0][31:0] rs1_data;
wire [31:0] rs2_data;
wire [31:0] next_PC;
wire ready;

2
hw/rtl/interfaces/VX_ifetch_req_if.v
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@@ -7,7 +7,7 @@ interface VX_ifetch_req_if ();
wire valid;
wire [`NUM_THREADS-1:0] thread_mask;
wire [`NW_BITS-1:0] warp_num;
wire [`NW_BITS-1:0] wid;
wire [31:0] curr_PC;
wire ready;

2
hw/rtl/interfaces/VX_ifetch_rsp_if.v
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@@ -7,7 +7,7 @@ interface VX_ifetch_rsp_if ();
wire valid;
wire [`NUM_THREADS-1:0] thread_mask;
wire [`NW_BITS-1:0] warp_num;
wire [`NW_BITS-1:0] wid;
wire [31:0] curr_PC;
wire [31:0] instr;
wire ready;

39
hw/rtl/interfaces/VX_issue_if.v Normal file
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@@ -0,0 +1,39 @@
`ifndef VX_ISSUE_IF
`define VX_ISSUE_IF
`include "VX_define.vh"
interface VX_issue_if ();
wire valid;
wire [`ISTAG_BITS-1:0] issue_tag;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] thread_mask;
wire [31:0] curr_PC;
wire [`EX_BITS-1:0] ex_type;
wire [`OP_BITS-1:0] ex_op;
wire [`FRM_BITS-1:0] frm;
wire wb;
wire [`NR_BITS-1:0] rd;
wire [`NUM_THREADS-1:0][31:0] rs1_data;
wire [`NUM_THREADS-1:0][31:0] rs2_data;
wire [`NUM_THREADS-1:0][31:0] rs3_data;
wire [`NR_BITS-1:0] rs1;
wire [31:0] imm;
wire rs1_is_PC;
wire rs2_is_imm;
wire [`NT_BITS-1:0] tid;
wire ready;
endinterface
`endif

2
hw/rtl/interfaces/VX_join_if.v
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@@ -6,7 +6,7 @@
interface VX_join_if ();
wire is_join;
wire [`NW_BITS-1:0] warp_num;
wire [`NW_BITS-1:0] wid;
endinterface

2
hw/rtl/interfaces/VX_lsu_req_if.v
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@@ -8,7 +8,7 @@ interface VX_lsu_req_if ();
wire valid;
wire [`NUM_THREADS-1:0] thread_mask;
wire [`ISTAG_BITS-1:0] issue_tag;
wire [`NW_BITS-1:0] warp_num;
wire [`NW_BITS-1:0] wid;
wire [31:0] curr_PC;
wire rw;

4
hw/rtl/interfaces/VX_mul_req_if.v
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@@ -12,11 +12,11 @@ interface VX_mul_req_if ();
wire valid;
wire [`ISTAG_BITS-1:0] issue_tag;
`DEBUG_BEGIN
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] thread_mask;
wire [`NW_BITS-1:0] warp_num;
wire [31:0] curr_PC;
`DEBUG_END
wire [`MUL_BITS-1:0] mul_op;
wire [`MUL_BITS-1:0] op;
wire [`NUM_THREADS-1:0][31:0] rs1_data;
wire [`NUM_THREADS-1:0][31:0] rs2_data;

22
hw/rtl/interfaces/VX_warp_ctl_if.v
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@@ -5,24 +5,12 @@
interface VX_warp_ctl_if ();
wire [`NW_BITS-1:0] warp_num;
wire [`NW_BITS-1:0] wid;
wire change_mask;
wire [`NUM_THREADS-1:0] thread_mask;
wire wspawn;
wire [31:0] wspawn_pc;
wire [`NUM_WARPS-1:0] wspawn_wmask;
wire is_barrier;
wire [`NB_BITS-1:0] barrier_id;
wire [`NW_BITS:0] barrier_num_warps;
wire is_split;
wire do_split;
wire [`NUM_THREADS-1:0] split_new_mask;
wire [`NUM_THREADS-1:0] split_later_mask;
wire [31:0] split_save_pc;
gpu_tmc_t tmc;
gpu_wspawn_t wspawn;
gpu_barrier_t barrier;
gpu_split_t split;
endinterface

6
hw/rtl/interfaces/VX_wb_if.v
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@@ -7,16 +7,14 @@ interface VX_wb_if ();
wire valid;
wire [`NUM_THREADS-1:0] thread_mask;
wire [`NW_BITS-1:0] warp_num;
wire [`NW_BITS-1:0] wid;
`IGNORE_WARNINGS_BEGIN
wire [31:0] curr_PC;
`IGNORE_WARNINGS_END
wire [`NR_BITS-1:0] rd;
wire [`NUM_THREADS-1:0][31:0] data;
wire ready;
wire [`NUM_THREADS-1:0][31:0] data;
endinterface

2
hw/rtl/interfaces/VX_wstall_if.v
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@@ -6,7 +6,7 @@
interface VX_wstall_if();
wire wstall;
wire [`NW_BITS-1:0] warp_num;
wire [`NW_BITS-1:0] wid;
endinterface