15 lines
299 B
Verilog
15 lines
299 B
Verilog
`ifndef VX_CSR_RSP_IF
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`define VX_CSR_RSP_IF
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`include "VX_define.vh"
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interface VX_csr_rsp_if ();
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wire valid;
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wire [`ISTAG_BITS-1:0] issue_tag;
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wire [`NUM_THREADS-1:0][31:0] data;
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wire ready;
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endinterface
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`endif |