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minor updates

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This commit is contained in:
Blaise Tine
2021-01-12 20:16:59 -08:00
parent f18ac24675
commit 464c4f4bd8
8 changed files with 16 additions and 13 deletions
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2
hw/opae/sources_16c.txt
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@@ -3,7 +3,7 @@
+define+SYNTHESIS +define+SYNTHESIS
+define+QUARTUS +define+QUARTUS
+define+FPU_FAST #+define+PERF_ENABLE
vortex_afu.json vortex_afu.json
QI:vortex_afu.qsf QI:vortex_afu.qsf

1
hw/opae/sources_1c.txt
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@@ -2,7 +2,6 @@
+define+SYNTHESIS +define+SYNTHESIS
+define+QUARTUS +define+QUARTUS
+define+FPU_FAST
#+define+SCOPE #+define+SCOPE
#+define+PERF_ENABLE #+define+PERF_ENABLE

2
hw/opae/sources_2c.txt
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@@ -2,7 +2,7 @@
+define+SYNTHESIS +define+SYNTHESIS
+define+QUARTUS +define+QUARTUS
+define+FPU_FAST #+define+PERF_ENABLE
vortex_afu.json vortex_afu.json
QI:vortex_afu.qsf QI:vortex_afu.qsf

2
hw/opae/sources_4c.txt
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@@ -2,7 +2,7 @@
+define+SYNTHESIS +define+SYNTHESIS
+define+QUARTUS +define+QUARTUS
+define+FPU_FAST #+define+PERF_ENABLE
vortex_afu.json vortex_afu.json
QI:vortex_afu.qsf QI:vortex_afu.qsf

3
hw/opae/sources_8c.txt
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@@ -1,8 +1,9 @@
+define+NUM_CORES=8 +define+NUM_CORES=8
+define+NUM_CLUSTERS=1
+define+SYNTHESIS +define+SYNTHESIS
+define+QUARTUS +define+QUARTUS
+define+FPU_FAST #+define+PERF_ENABLE
vortex_afu.json vortex_afu.json
QI:vortex_afu.qsf QI:vortex_afu.qsf

10
hw/rtl/afu/vortex_afu.sv
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@@ -934,6 +934,8 @@ Vortex #() vortex (
`ifdef SCOPE `ifdef SCOPE
`SCOPE_ASSIGN (cmd_type, cmd_type);
`SCOPE_ASSIGN (state, state);
`SCOPE_ASSIGN (ccip_sRxPort_c0_mmioRdValid, cp2af_sRxPort.c0.mmioRdValid); `SCOPE_ASSIGN (ccip_sRxPort_c0_mmioRdValid, cp2af_sRxPort.c0.mmioRdValid);
`SCOPE_ASSIGN (ccip_sRxPort_c0_mmioWrValid, cp2af_sRxPort.c0.mmioWrValid); `SCOPE_ASSIGN (ccip_sRxPort_c0_mmioWrValid, cp2af_sRxPort.c0.mmioWrValid);
`SCOPE_ASSIGN (mmio_hdr_address, mmio_hdr.address); `SCOPE_ASSIGN (mmio_hdr_address, mmio_hdr.address);
@@ -966,10 +968,10 @@ Vortex #() vortex (
wire scope_changed = `SCOPE_TRIGGER; wire scope_changed = `SCOPE_TRIGGER;
VX_scope #( VX_scope #(
.DATAW ($bits({`SCOPE_DATA_LIST,`SCOPE_UPDATE_LIST})), .DATAW ($bits({`SCOPE_DATA_LIST,`SCOPE_UPDATE_LIST})),
.BUSW (64), .BUSW (64),
.SIZE (`SCOPE_SIZE), .SIZE (`SCOPE_SIZE),
.UPDW ($bits({`SCOPE_UPDATE_LIST})) .UPDW ($bits({`SCOPE_UPDATE_LIST}))
) scope ( ) scope (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),

5
hw/rtl/cache/VX_bank.v vendored
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@@ -238,12 +238,11 @@ module VX_bank #(
wire is_mshr_miss_st1 = valid_st1 && is_mshr_st1 && (miss_st1 || force_miss_st1); wire is_mshr_miss_st1 = valid_st1 && is_mshr_st1 && (miss_st1 || force_miss_st1);
// determine which queue to pop next in piority order // determine which queue to pop next in piority order
wire mshr_pop_unqual = mshr_valid; wire mshr_pop_unqual = mshr_valid && !is_mshr_miss_st1;
wire drsq_pop_unqual = !mshr_pop_unqual && !drsq_empty; wire drsq_pop_unqual = !mshr_pop_unqual && !drsq_empty;
wire creq_pop_unqual = !mshr_pop_unqual && !drsq_pop_unqual && !creq_empty && !mshr_almost_full && !dreq_almost_full; wire creq_pop_unqual = !mshr_pop_unqual && !drsq_pop_unqual && !creq_empty && !mshr_almost_full && !dreq_almost_full;
assign mshr_pop = mshr_pop_unqual && !pipeline_stall assign mshr_pop = mshr_pop_unqual && !pipeline_stall;
&& !is_mshr_miss_st1; // stop if previous request was a miss
assign drsq_pop = drsq_pop_unqual && !pipeline_stall; assign drsq_pop = drsq_pop_unqual && !pipeline_stall;
assign creq_pop = creq_pop_unqual && !pipeline_stall; assign creq_pop = creq_pop_unqual && !pipeline_stall;

2
hw/scripts/scope.json
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@@ -74,6 +74,8 @@
}, },
"taps": { "taps": {
"afu": { "afu": {
"!cmd_type":3,
"!state":3,
"?ccip_sRxPort_c0_mmioRdValid":1, "?ccip_sRxPort_c0_mmioRdValid":1,
"?ccip_sRxPort_c0_mmioWrValid":1, "?ccip_sRxPort_c0_mmioWrValid":1,
"mmio_hdr_address":16, "mmio_hdr_address":16,