diff --git a/hw/opae/sources_16c.txt b/hw/opae/sources_16c.txt
index 637db1ac..987404f0 100644
--- a/hw/opae/sources_16c.txt
+++ b/hw/opae/sources_16c.txt
@@ -3,7 +3,7 @@
 
 +define+SYNTHESIS
 +define+QUARTUS
-+define+FPU_FAST
+#+define+PERF_ENABLE
 
 vortex_afu.json
 QI:vortex_afu.qsf
diff --git a/hw/opae/sources_1c.txt b/hw/opae/sources_1c.txt
index 4671c87a..6e96357a 100644
--- a/hw/opae/sources_1c.txt
+++ b/hw/opae/sources_1c.txt
@@ -2,7 +2,6 @@
 
 +define+SYNTHESIS
 +define+QUARTUS
-+define+FPU_FAST
 #+define+SCOPE
 #+define+PERF_ENABLE
 
diff --git a/hw/opae/sources_2c.txt b/hw/opae/sources_2c.txt
index ef988ec6..a70589f5 100644
--- a/hw/opae/sources_2c.txt
+++ b/hw/opae/sources_2c.txt
@@ -2,7 +2,7 @@
 
 +define+SYNTHESIS
 +define+QUARTUS
-+define+FPU_FAST
+#+define+PERF_ENABLE
 
 vortex_afu.json
 QI:vortex_afu.qsf
diff --git a/hw/opae/sources_4c.txt b/hw/opae/sources_4c.txt
index fa3b1aa2..9ac95cdd 100644
--- a/hw/opae/sources_4c.txt
+++ b/hw/opae/sources_4c.txt
@@ -2,7 +2,7 @@
 
 +define+SYNTHESIS
 +define+QUARTUS
-+define+FPU_FAST
+#+define+PERF_ENABLE
 
 vortex_afu.json
 QI:vortex_afu.qsf
diff --git a/hw/opae/sources_8c.txt b/hw/opae/sources_8c.txt
index fa02d08c..ad53786c 100644
--- a/hw/opae/sources_8c.txt
+++ b/hw/opae/sources_8c.txt
@@ -1,8 +1,9 @@
 +define+NUM_CORES=8
++define+NUM_CLUSTERS=1
 
 +define+SYNTHESIS
 +define+QUARTUS
-+define+FPU_FAST
+#+define+PERF_ENABLE
 
 vortex_afu.json
 QI:vortex_afu.qsf
diff --git a/hw/rtl/afu/vortex_afu.sv b/hw/rtl/afu/vortex_afu.sv
index 37c7d07d..570eab1b 100644
--- a/hw/rtl/afu/vortex_afu.sv
+++ b/hw/rtl/afu/vortex_afu.sv
@@ -934,6 +934,8 @@ Vortex #() vortex (
 
 `ifdef SCOPE
 
+`SCOPE_ASSIGN (cmd_type, cmd_type);
+`SCOPE_ASSIGN (state, state);
 `SCOPE_ASSIGN (ccip_sRxPort_c0_mmioRdValid, cp2af_sRxPort.c0.mmioRdValid);
 `SCOPE_ASSIGN (ccip_sRxPort_c0_mmioWrValid, cp2af_sRxPort.c0.mmioWrValid);
 `SCOPE_ASSIGN (mmio_hdr_address, mmio_hdr.address);
@@ -966,10 +968,10 @@ Vortex #() vortex (
 wire scope_changed = `SCOPE_TRIGGER;
 
 VX_scope #(
-  .DATAW    ($bits({`SCOPE_DATA_LIST,`SCOPE_UPDATE_LIST})),
-  .BUSW     (64),
-  .SIZE     (`SCOPE_SIZE),
-  .UPDW     ($bits({`SCOPE_UPDATE_LIST}))
+  .DATAW ($bits({`SCOPE_DATA_LIST,`SCOPE_UPDATE_LIST})),
+  .BUSW  (64),
+  .SIZE  (`SCOPE_SIZE),
+  .UPDW  ($bits({`SCOPE_UPDATE_LIST}))
 ) scope (
   .clk      (clk),
   .reset    (reset),
diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v
index 6682933a..0d6491d2 100644
--- a/hw/rtl/cache/VX_bank.v
+++ b/hw/rtl/cache/VX_bank.v
@@ -237,13 +237,12 @@ module VX_bank #(
 
     wire is_mshr_miss_st1 = valid_st1 && is_mshr_st1 && (miss_st1 || force_miss_st1);
 
-    // determine which queue to pop next in piority order
-    wire mshr_pop_unqual = mshr_valid;
+    // determine which queue to pop next in piority order    
+    wire mshr_pop_unqual = mshr_valid && !is_mshr_miss_st1;
     wire drsq_pop_unqual = !mshr_pop_unqual && !drsq_empty;
     wire creq_pop_unqual = !mshr_pop_unqual && !drsq_pop_unqual && !creq_empty && !mshr_almost_full && !dreq_almost_full;
 
-    assign mshr_pop = mshr_pop_unqual && !pipeline_stall 
-                   && !is_mshr_miss_st1; // stop if previous request was a miss
+    assign mshr_pop = mshr_pop_unqual && !pipeline_stall;
     assign drsq_pop = drsq_pop_unqual && !pipeline_stall;
     assign creq_pop = creq_pop_unqual && !pipeline_stall;
 
diff --git a/hw/scripts/scope.json b/hw/scripts/scope.json
index 4dc38645..e1abfccf 100644
--- a/hw/scripts/scope.json
+++ b/hw/scripts/scope.json
@@ -74,6 +74,8 @@
     },
     "taps": {     
         "afu": {                                     
+            "!cmd_type":3,
+            "!state":3,
             "?ccip_sRxPort_c0_mmioRdValid":1,
             "?ccip_sRxPort_c0_mmioWrValid":1,
             "mmio_hdr_address":16,