From 1b9d9f36256517d8acd8d71d47e481db1f92971c Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Tue, 31 Mar 2020 20:23:09 -0700 Subject: [PATCH] Fixed incorrect miss_add on pipeline stall --- rtl/VX_cache/VX_bank.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rtl/VX_cache/VX_bank.v b/rtl/VX_cache/VX_bank.v index 3fc36692..9dcd8d03 100644 --- a/rtl/VX_cache/VX_bank.v +++ b/rtl/VX_cache/VX_bank.v @@ -524,7 +524,7 @@ module VX_bank wire invalidate_fill; // Enqueue to miss reserv if it's a valid miss - assign miss_add = valid_st2 && !is_snp_st2 && miss_st2 && !mrvq_full && !((is_snp_st2 && valid_st2 && ffsq_full) ||((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full)); + assign miss_add = valid_st2 && !is_snp_st2 && miss_st2 && !mrvq_full && !((is_snp_st2 && valid_st2 && ffsq_full) ||((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full)); assign miss_add_pc = pc_st2; assign miss_add_addr = addr_st2; assign miss_add_data = writeword_st2;