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This commit is contained in:
Blaise Tine
2020-08-22 00:22:04 -07:00
parent 6c12391338
commit 0b355f228e
80 changed files with 1811 additions and 1528 deletions
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17
hw/rtl/interfaces/VX_alu_req_if.v
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@@ -5,23 +5,20 @@
interface VX_alu_req_if ();
wire valid;
wire [`ISTAG_BITS-1:0] issue_tag;
`DEBUG_BEGIN
wire [`NW_BITS-1:0] wid;
wire valid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] thread_mask;
`DEBUG_END
wire [31:0] curr_PC;
wire [`ALU_BITS-1:0] op;
wire [`ALU_BR_BITS-1:0] op;
wire rs1_is_PC;
wire rs2_is_imm;
wire [31:0] imm;
wire [`NT_BITS-1:0] tid;
wire [`NUM_THREADS-1:0][31:0] rs1_data;
wire [`NUM_THREADS-1:0][31:0] rs2_data;
wire [`NR_BITS-1:0] rd;
wire wb;
wire ready;

29
hw/rtl/interfaces/VX_bru_req_if.v
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@@ -1,29 +0,0 @@
`ifndef VX_BRANCH_REQ_IF
`define VX_BRANCH_REQ_IF
`include "VX_define.vh"
interface VX_bru_req_if ();
wire valid;
wire [`ISTAG_BITS-1:0] issue_tag;
wire [`NW_BITS-1:0] wid;
`DEBUG_BEGIN
wire [`NUM_THREADS-1:0] thread_mask;
`DEBUG_END
wire [31:0] curr_PC;
wire [`BRU_BITS-1:0] op;
wire rs1_is_PC;
wire [31:0] rs1_data;
wire [31:0] rs2_data;
wire [31:0] offset;
wire ready;
endinterface
`endif

36
hw/rtl/interfaces/VX_cmt_to_issue_if.v
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@@ -1,36 +0,0 @@
`ifndef VX_CMT_TO_ISSUE_IF
`define VX_CMT_TO_ISSUE_IF
`include "VX_define.vh"
interface VX_cmt_to_issue_if ();
wire alu_valid;
wire bru_valid;
wire lsu_valid;
wire csr_valid;
wire mul_valid;
wire fpu_valid;
wire gpu_valid;
wire [`ISTAG_BITS-1:0] alu_tag;
wire [`ISTAG_BITS-1:0] bru_tag;
wire [`ISTAG_BITS-1:0] lsu_tag;
wire [`ISTAG_BITS-1:0] csr_tag;
wire [`ISTAG_BITS-1:0] mul_tag;
wire [`ISTAG_BITS-1:0] fpu_tag;
wire [`ISTAG_BITS-1:0] gpu_tag;
`IGNORE_WARNINGS_BEGIN
issue_data_t alu_data;
issue_data_t bru_data;
issue_data_t lsu_data;
issue_data_t csr_data;
issue_data_t mul_data;
issue_data_t fpu_data;
issue_data_t gpu_data;
`IGNORE_WARNINGS_END
endinterface
`endif

11
hw/rtl/interfaces/VX_csr_req_if.v
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@@ -6,18 +6,13 @@
interface VX_csr_req_if ();
wire valid;
wire [`ISTAG_BITS-1:0] issue_tag;
wire [`NW_BITS-1:0] wid;
`DEBUG_BEGIN
wire [`NUM_THREADS-1:0] thread_mask;
`DEBUG_END
wire [31:0] curr_PC;
wire [31:0] curr_PC;
wire [`CSR_BITS-1:0] op;
wire [`CSR_ADDR_BITS-1:0] csr_addr;
wire [31:0] csr_mask;
wire [`NR_BITS-1:0] rd;
wire wb;
wire is_io;
@@ -26,4 +21,4 @@ interface VX_csr_req_if ();
endinterface
`endif
`endif

15
hw/rtl/interfaces/VX_csr_rsp_if.v
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@@ -1,15 +0,0 @@
`ifndef VX_CSR_RSP_IF
`define VX_CSR_RSP_IF
`include "VX_define.vh"
interface VX_csr_rsp_if ();
wire valid;
wire [`ISTAG_BITS-1:0] issue_tag;
wire [`NUM_THREADS-1:0][31:0] data;
wire ready;
endinterface
`endif

6
hw/rtl/interfaces/VX_csr_to_fpu_if.v → hw/rtl/interfaces/VX_csr_to_issue_if.v
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@@ -1,5 +1,5 @@
`ifndef VX_CSR_TO_FPU_IF
`define VX_CSR_TO_FPU_IF
`ifndef VX_CSR_TO_ISSUE_IF
`define VX_CSR_TO_ISSUE_IF
`include "VX_define.vh"
@@ -7,7 +7,7 @@
`IGNORE_WARNINGS_BEGIN
`endif
interface VX_csr_to_fpu_if ();
interface VX_csr_to_issue_if ();
wire [`NW_BITS-1:0] wid;
wire [`FRM_BITS-1:0] frm;

15
hw/rtl/interfaces/VX_decode_if.v
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@@ -6,29 +6,26 @@
interface VX_decode_if ();
wire valid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] thread_mask;
wire [31:0] curr_PC;
wire [`EX_BITS-1:0] ex_type;
wire [`OP_BITS-1:0] ex_op;
wire [`FRM_BITS-1:0] frm;
wire wb;
wire [`NR_BITS-1:0] rd;
wire [`NR_BITS-1:0] rs1;
wire [`NR_BITS-1:0] rs2;
wire [`NR_BITS-1:0] rs3;
wire [31:0] imm;
wire rs1_is_PC;
wire rs2_is_imm;
wire [`NUM_REGS-1:0] reg_use_mask;
// FP states
wire [`NR_BITS-1:0] rs3;
wire rs2_is_imm;
wire use_rs3;
wire [`FRM_BITS-1:0] frm;
wire wb;
wire [`NUM_REGS-1:0] used_regs;
wire ready;

11
hw/rtl/interfaces/VX_exu_to_cmt_if.v
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@@ -5,9 +5,14 @@
interface VX_exu_to_cmt_if ();
wire valid;
wire [`ISTAG_BITS-1:0] issue_tag;
wire [`NUM_THREADS-1:0][31:0] data;
wire valid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] thread_mask;
wire [31:0] curr_PC;
wire [`NUM_THREADS-1:0][31:0] data;
wire [`NR_BITS-1:0] rd;
wire wb;
wire ready;
endinterface

10
hw/rtl/interfaces/VX_fpu_req_if.v
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@@ -10,20 +10,18 @@
interface VX_fpu_req_if ();
wire valid;
wire [`ISTAG_BITS-1:0] issue_tag;
wire [`NW_BITS-1:0] wid;
`DEBUG_BEGIN
wire [`NUM_THREADS-1:0] thread_mask;
wire [31:0] curr_PC;
`DEBUG_END
wire [`FPU_BITS-1:0] op;
wire [`FRM_BITS-1:0] frm;
wire [`NUM_THREADS-1:0][31:0] rs1_data;
wire [`NUM_THREADS-1:0][31:0] rs2_data;
wire [`NUM_THREADS-1:0][31:0] rs3_data;
wire [`NR_BITS-1:0] rd;
wire wb;
wire ready;
endinterface

15
hw/rtl/interfaces/VX_fpu_to_cmt_if.v
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@@ -5,11 +5,16 @@
interface VX_fpu_to_cmt_if ();
wire valid;
wire [`ISTAG_BITS-1:0] issue_tag;
wire [`NUM_THREADS-1:0][31:0] data;
wire has_fflags;
fflags_t [`NUM_THREADS-1:0] fflags;
wire valid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] thread_mask;
wire [31:0] curr_PC;
wire [`NUM_THREADS-1:0][31:0] data;
wire [`NR_BITS-1:0] rd;
wire wb;
wire has_fflags;
fflags_t [`NUM_THREADS-1:0] fflags;
wire ready;
endinterface

3
hw/rtl/interfaces/VX_gpr_read_if.v
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@@ -19,7 +19,8 @@ interface VX_gpr_read_if ();
wire [`NUM_THREADS-1:0][31:0] rs2_data;
wire [`NUM_THREADS-1:0][31:0] rs3_data;
wire ready;
wire ready_in;
wire ready_out;
endinterface

6
hw/rtl/interfaces/VX_gpu_req_if.v
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@@ -6,15 +6,15 @@
interface VX_gpu_req_if();
wire valid;
wire [`ISTAG_BITS-1:0] issue_tag;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] thread_mask;
wire [31:0] curr_PC;
wire [`GPU_BITS-1:0] op;
wire [`NUM_THREADS-1:0][31:0] rs1_data;
wire [31:0] rs2_data;
wire [`NR_BITS-1:0] rd;
wire wb;
wire ready;

39
hw/rtl/interfaces/VX_issue_if.v
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@@ -1,39 +0,0 @@
`ifndef VX_ISSUE_IF
`define VX_ISSUE_IF
`include "VX_define.vh"
interface VX_issue_if ();
wire valid;
wire [`ISTAG_BITS-1:0] issue_tag;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] thread_mask;
wire [31:0] curr_PC;
wire [`EX_BITS-1:0] ex_type;
wire [`OP_BITS-1:0] ex_op;
wire [`FRM_BITS-1:0] frm;
wire wb;
wire [`NR_BITS-1:0] rd;
wire [`NUM_THREADS-1:0][31:0] rs1_data;
wire [`NUM_THREADS-1:0][31:0] rs2_data;
wire [`NUM_THREADS-1:0][31:0] rs3_data;
wire [`NR_BITS-1:0] rs1;
wire [31:0] imm;
wire rs1_is_PC;
wire rs2_is_imm;
wire [`NT_BITS-1:0] tid;
wire ready;
endinterface
`endif

4
hw/rtl/interfaces/VX_lsu_req_if.v
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@@ -6,9 +6,9 @@
interface VX_lsu_req_if ();
wire valid;
wire [`NUM_THREADS-1:0] thread_mask;
wire [`ISTAG_BITS-1:0] issue_tag;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] thread_mask;
wire [31:0] curr_PC;
wire rw;

7
hw/rtl/interfaces/VX_mul_req_if.v
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@@ -10,16 +10,15 @@
interface VX_mul_req_if ();
wire valid;
wire [`ISTAG_BITS-1:0] issue_tag;
`DEBUG_BEGIN
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] thread_mask;
wire [31:0] curr_PC;
`DEBUG_END
wire [`MUL_BITS-1:0] op;
wire [`NUM_THREADS-1:0][31:0] rs1_data;
wire [`NUM_THREADS-1:0][31:0] rs2_data;
wire [`NR_BITS-1:0] rd;
wire wb;
wire ready;

1
hw/rtl/interfaces/VX_warp_ctl_if.v
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@@ -5,6 +5,7 @@
interface VX_warp_ctl_if ();
wire valid;
wire [`NW_BITS-1:0] wid;
gpu_tmc_t tmc;

8
hw/rtl/interfaces/VX_wb_if.v → hw/rtl/interfaces/VX_writeback_if.v
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@@ -1,9 +1,9 @@
`ifndef VX_WB_IF
`define VX_WB_IF
`ifndef VX_WRITEBACK_IF
`define VX_WRITEBACK_IF
`include "VX_define.vh"
interface VX_wb_if ();
interface VX_writeback_if ();
wire valid;
wire [`NUM_THREADS-1:0] thread_mask;
@@ -16,6 +16,8 @@ interface VX_wb_if ();
wire [`NR_BITS-1:0] rd;
wire [`NUM_THREADS-1:0][31:0] data;
wire ready;
endinterface
`endif