27 lines
639 B
Verilog
27 lines
639 B
Verilog
`ifndef VX_ALU_REQ_IF
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`define VX_ALU_REQ_IF
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`include "VX_define.vh"
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interface VX_alu_req_if ();
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wire valid;
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wire [`NW_BITS-1:0] wid;
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wire [`NUM_THREADS-1:0] thread_mask;
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wire [31:0] curr_PC;
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wire [`ALU_BR_BITS-1:0] op;
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wire rs1_is_PC;
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wire rs2_is_imm;
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wire [31:0] imm;
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wire [`NT_BITS-1:0] tid;
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wire [`NUM_THREADS-1:0][31:0] rs1_data;
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wire [`NUM_THREADS-1:0][31:0] rs2_data;
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wire [`NR_BITS-1:0] rd;
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wire wb;
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wire ready;
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endinterface
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`endif |