c1e8f4ef86
The Verilog wrapper maintains the cycle state, and C parser becomes a
combinational logic which Verilog queries to check if there is a request
in the trace at a specific {cycle, core_id, thread_id}.
99 lines
2.7 KiB
Verilog
99 lines
2.7 KiB
Verilog
`define DATA_WIDTH 64
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`define MAX_NUM_THREADS 32
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import "DPI-C" function void memtrace_init(
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input string filename
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);
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// Make sure to sync the parameters for:
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// (1) import "DPI-C" declaration
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// (2) C function declaration
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// (3) DPI function calls inside initial/always blocks
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import "DPI-C" function void memtrace_tick
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(
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input bit trace_read_ready,
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input longint trace_read_cycle,
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input int trace_read_tid,
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output bit trace_read_valid,
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output longint trace_read_address,
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output bit trace_read_finished
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);
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module SimMemTrace #(parameter NUM_THREADS = 4) (
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input clock,
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input reset,
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// These have to match the IO port of the Chisel wrapper module.
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input trace_read_ready,
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output trace_read_valid,
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output [`DATA_WIDTH*NUM_THREADS-1:0] trace_read_address,
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output trace_read_finished
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);
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bit __in_valid;
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longint __in_address[NUM_THREADS-1:0];
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bit __in_finished;
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string __uartlog;
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// Cycle counter that is used to query C parser whether we have a request
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// coming in at the current cycle.
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reg [`DATA_WIDTH-1:0] cycle_counter;
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// registers that stage outputs of the C parser
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reg __in_valid_reg;
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reg [`DATA_WIDTH-1:0] __in_address_reg [NUM_THREADS-1:0];
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reg __in_finished_reg;
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genvar g;
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assign trace_read_valid = __in_valid_reg;
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generate
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for (g = 0; g < NUM_THREADS; g = g + 1) begin
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assign trace_read_address[`DATA_WIDTH*(g+1)-1:`DATA_WIDTH*g] = __in_address_reg[g];
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end
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endgenerate
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assign trace_read_finished = __in_finished_reg;
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initial begin
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/* $value$plusargs("uartlog=%s", __uartlog); */
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memtrace_init("vecadd.core1.thread4.trace");
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end
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// Evaluate the signals on the positive edge
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always @(posedge clock) begin
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if (reset) begin
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__in_valid = 1'b0;
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for (integer tid = 0; tid < NUM_THREADS; tid = tid + 1) begin
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__in_address[tid] = `DATA_WIDTH'b0;
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end
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__in_finished = 1'b0;
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cycle_counter <= `DATA_WIDTH'b0;
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__in_valid_reg <= 1'b0;
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for (integer tid = 0; tid < NUM_THREADS; tid = tid + 1) begin
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__in_address_reg[tid] <= `DATA_WIDTH'b0;
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end
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__in_finished_reg <= 1'b0;
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end else begin
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cycle_counter <= cycle_counter + 1'b1;
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for (integer tid = 0; tid < NUM_THREADS; tid = tid + 1) begin
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memtrace_tick(
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trace_read_ready,
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cycle_counter,
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tid,
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__in_valid,
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__in_address[tid],
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__in_finished
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);
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end
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__in_valid_reg <= __in_valid;
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for (integer tid = 0; tid < NUM_THREADS; tid = tid + 1) begin
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__in_address_reg[tid] <= __in_address[tid];
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end
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__in_finished_reg <= __in_finished;
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end
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end
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endmodule
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