Hansung Kim c1e8f4ef86 Maintain cycle inside Verilog instead of C
The Verilog wrapper maintains the cycle state, and C parser becomes a
combinational logic which Verilog queries to check if there is a request
in the trace at a specific {cycle, core_id, thread_id}.
2023-03-03 16:38:32 -08:00
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1.5 MiB
Languages
Scala 91.6%
C++ 3.9%
Verilog 3.6%
Makefile 0.9%