6 Commits

Author	SHA1	Message	Date
Hansung Kim	c1e8f4ef86	Maintain cycle inside Verilog instead of C ... The Verilog wrapper maintains the cycle state, and C parser becomes a combinational logic which Verilog queries to check if there is a request in the trace at a specific {cycle, core_id, thread_id}.	2023-03-03 16:38:32 -08:00
Hansung Kim	664959f723	Parameterize SimMemTrace Verilog module to number of threads	2023-03-03 16:16:07 -08:00
Hansung Kim	9025729c0e	Emit address in addition to cycle	2023-02-27 17:36:54 -08:00
Hansung Kim	0ebaed5f1b	Communicate trace cycle data from C++ to Chisel	2023-02-27 14:40:49 -08:00
Hansung Kim	72de4bca66	Initial parsing of memory trace file in C++	2023-02-27 13:47:30 -08:00
Hansung Kim	80e4b5c734	Set up simple DPI for trace-driven testing	2023-02-26 20:39:19 -08:00