Richard Yan
c655874470
width widget in DummyCoalescingUnitTB
2023-04-28 20:47:47 -07:00
Richard Yan
900f5adb20
running coalescing flow
2023-04-26 01:23:21 -07:00
Richard Yan
99348e1e40
mostly running coalescing test
2023-04-25 02:50:14 -07:00
Richard Yan
3a0fdb2c67
WIP diplomacy set up for coal unit test
2023-04-25 02:26:13 -07:00
Richard Yan
be40c77d06
merge graphics
2023-04-25 00:10:51 -07:00
Richard Yan
37620400db
WIP coalescing flow test
2023-04-25 00:09:23 -07:00
Hansung Kim
31e04e9402
Fix CoalShiftQueue invalidate logic
...
IO type change to Valid[UInt] was not reflected in the valid bit logic.
2023-04-24 14:01:39 -07:00
Hansung Kim
7539c39c45
Store SizeEnum in entry instead of UInt
2023-04-23 22:34:19 -07:00
Hansung Kim
0f2e4ee8aa
Store UInt instead of ChiselEnum in entry; pass tests
...
Scala isn't happy with storing ChiselEnum type for some reason
2023-04-23 15:28:12 -07:00
Hansung Kim
8cee61a591
Uncoalesce using table size enum
2023-04-23 14:42:10 -07:00
Hansung Kim
ccf9b95fb5
Create custom response bundle to decouple from TileLink
...
... and easier unit testing.
2023-04-23 13:37:10 -07:00
Hansung Kim
6ae08b6541
Add missing sizeWidth to uncoalescer test
2023-04-21 11:24:57 -07:00
Hansung Kim
de6d6eee1a
Fix request shift queue not enqueuing when empty
...
The queue was enabling shifting of the registers whenever deq.ready
was 1, even when the queue was empty. This caused `wen` to disable
writing enq.bits to any of the entries in the queue. Fixed by setting
`shift` to 0 when queue is empty.
2023-04-20 21:12:19 -07:00
Hansung Kim
abecd30b2b
Store sourceId for every old req entry in table
2023-04-07 14:50:40 -07:00
Hansung Kim
d62732fb89
Invalidate outgoing per-lane requests that got coalesced
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Now the response queue no longer blocks the flow!
2023-04-01 14:33:46 -07:00
Hansung Kim
d9f6e27a04
Move coalescer chiseltest to its own package
2023-03-31 20:51:34 -07:00
Hansung Kim
4aabbecda1
Do not deassert deq.valid right after invalidate(head)
...
... to avoid combinational cycle.
2023-03-31 20:40:12 -07:00
Hansung Kim
1c0c8fa112
Complete test for enqueuing to invalidated tail
2023-03-31 20:15:49 -07:00
Hansung Kim
3ee639f376
Eliminate unnecessary delay when invalidating head
...
When invalidate signal is given for queue head, that head should be
gone immediately at the next cycle, regardless of what deq.ready was
at the previous cycle.
2023-03-31 19:55:36 -07:00
Hansung Kim
6ca22a39e0
Implement automatic dequeuing of invalid entries
2023-03-31 19:40:10 -07:00
Hansung Kim
f44dfc8d5a
Implement invalidation for the queue
2023-03-31 19:25:45 -07:00
Hansung Kim
a0d75530cb
Use used mask in CoalShiftQueue
...
Easier to use than wptr when enqueuing & dequeueing at the same time.
2023-03-31 17:10:09 -07:00
Hansung Kim
303c43a5e2
Make CoalShiftQueue use wptr; add unit test
...
Cannot solely rely on valid mask because there may be holes in the
middle.
2023-03-29 19:06:08 -07:00
Hansung Kim
12b3b67687
Store multiple oldSrcId reqs per lane in a table row
...
The number of the per-lane reqs is controlled by `numPerLaneReqs`
rather than being set to 2 ** sourceWidth to allow some flexibility.
2023-03-29 14:02:41 -07:00
Hansung Kim
3b335bda18
Basic unit test for the uncoalescer
2023-03-29 00:50:13 -07:00
Hansung Kim
9bc8f0074b
Make uncoalescer a separate module for better testability
2023-03-28 17:07:54 -07:00
Hansung Kim
23d8fa3be1
Write simple test for MultiPortQueue
...
... and comment out old CAM-based inflight table test.
2023-03-27 15:21:01 -07:00
Hansung Kim
2e06898dc0
Handle enqueue and lookup at the same cycle
...
This fixes the inflight table filling up to full after some time in the
memtrace simulation.
2023-03-13 16:22:22 -07:00
Hansung Kim
400b356cfb
Fix lookup succeeding on invalid entry; add test case
...
also enable VCS FSDB annotation in chiseltest
2023-03-12 03:26:09 -07:00
Hansung Kim
6de95587de
Add chiseltest for inflight table
2023-03-11 23:20:50 -08:00
