Richard Yan
63b0bfdcd3
bump vortex
2024-05-08 11:32:12 -07:00
Richard Yan
c5c4b3eb8b
bump vortex
2024-05-07 14:00:43 -07:00
Hansung Kim
9b2846fcee
Bump vortex to tensor_core merge
2024-05-02 16:18:51 -07:00
Richard Yan
bb8575252e
changes for synthesis
2024-04-17 18:09:48 -07:00
Richard Yan
c2fbe8388e
route aligned smem requests separately, fix node bugs
2024-04-09 20:07:58 -07:00
Hansung Kim
20a33e5a40
Bump vortex
2024-03-21 15:45:56 -07:00
Hansung Kim
785dcc9df7
Bump vortex
2024-03-18 14:32:06 -07:00
Hansung Kim
9024048a52
Bump vortex
2024-03-17 14:13:33 -07:00
Hansung Kim
92069099a2
Bump vortex with LSU fix
2024-03-14 16:47:39 -07:00
Hansung Kim
eca3619380
Bump vortex
2024-03-07 17:44:21 -08:00
Hansung Kim
7aacd21b42
Bump vortex with upstream merge
2024-03-07 15:01:15 -08:00
Hansung Kim
6d2f89c6ae
Remaining renames
2024-02-05 09:44:55 -08:00
Hansung Kim
16c4292e57
Rename core.io.cease to finished; bump vortex
2024-01-26 14:25:12 -08:00
Hansung Kim
78075e5148
Bump vortex
2024-01-25 23:24:05 -08:00
Hansung Kim
34fce0e34d
Commented out TLRAMCoalescerFuzzer test module
2024-01-23 13:47:22 -08:00
Hansung Kim
164e722790
Pass inflight to DPI to determine proper fuzz termination
2024-01-23 01:11:52 -08:00
Hansung Kim
b2a83c788e
Pass both A and D bundles to memfuzzer DPI
2024-01-22 01:54:45 -08:00
Hansung Kim
e7340ba840
Use negedge for DPI calls to avoid confusion
2024-01-22 01:51:35 -08:00
Hansung Kim
e183606193
Write basic DPI mem fuzzer
2024-01-20 21:47:06 -08:00
Hansung Kim
6ff127eb51
Write faux memory fuzzer
2024-01-19 22:37:44 -08:00
Hansung Kim
69bf554d0f
Split SimMem verilog constants to a .vh file
2024-01-19 18:25:03 -08:00
Hansung Kim
7914607304
Bump vortex with IBUF/LSUQ size change
2024-01-16 23:54:39 -08:00
Richard Yan
dea005a179
incorporate vortex2
2024-01-16 17:41:33 -08:00
Richard Yan
f9b7e9fbe4
restructure from rocket-chip to radiance
2024-01-16 16:21:50 -08:00
Richard Yan
c742a13c1e
restructure: initial filter pass
2024-01-11 10:08:43 -08:00
Hansung Kim
0bb8e6d705
Bump vortex with ibuffer size fix
2023-11-10 18:38:59 -08:00
Vamber Yang
75adb1dc66
Intergation of L1 Fatbank
2023-10-31 16:14:34 -07:00
Hansung Kim
1e8cc5ef90
Bump vortex
2023-10-25 20:07:20 -07:00
Hansung Kim
805abd1b4b
Bump vortex for TL port change
2023-10-18 20:05:55 -07:00
Hansung Kim
fb97bd3c2b
Decouple Vortex imem bundle from TL
2023-10-17 12:18:58 -07:00
Hansung Kim
e4dd0c21e9
Bump vortex
2023-10-16 20:45:18 -07:00
Richard Yan
dd194ca61d
bump vortex
2023-10-13 15:25:49 -07:00
Hansung Kim
b7a7a7a0a7
Bump vortex
2023-10-11 20:32:08 -07:00
joshua
127d7613e1
add vortex fat bank + test (not compiling atm)
2023-10-09 14:49:57 -07:00
Hansung Kim
c368e92ddb
Bump vortex
2023-10-06 21:31:22 -07:00
Hansung Kim
e7a008ec74
Rename #define constants in SimMemTrace
...
... to prevent collision with constants of the same name in other
verilog sources.
2023-10-01 20:58:49 -07:00
Hansung Kim
5ee4154f26
Fix C/verilog argument size mismatch on Verilator
2023-10-01 12:12:11 -07:00
joshua
a98ec2758e
bump vortex
2023-09-29 00:52:23 -07:00
Richard Yan
f0f395661d
bump vortex
2023-09-27 10:53:38 -07:00
Richard Yan
0f47ae078e
add operand roms, bump vortex
2023-09-25 21:27:13 -07:00
Richard Yan
7c5281cd0e
multilane support, args.bin ROM, verilog sources cleanup and vortex bump
2023-09-15 11:16:55 -07:00
Richard Yan
d392d76608
bump vortex and increase source ids
2023-09-11 14:06:08 -07:00
Richard Yan
43f95175f1
bump verilog sources, remove files and mem changes
2023-09-09 01:55:02 -07:00
Richard Yan
8cef2ae135
integrate vortex as tile
2023-09-08 14:25:37 -07:00
Hansung Kim
e40b7f0b8b
Support receiving trace filename from VPI for loggers
...
Useful for testing with different memtraces without having to recompile
design. This worked before for the trace driver but not for trace
logger.
Usage: make CONFIG=MemtraceCoreConfig run-binary-debug BINARY=none \
EXTRA_SIM_FLAGS="+memtracefile=nvbit.vecadd.n100000.filter_sm0.lane4.broken.trace"
2023-05-28 22:15:32 -07:00
Vamber Yang
9ecace676c
Add useful error msg
2023-05-19 17:47:40 -07:00
Hansung Kim
1886aefcc1
Parameterize tracefile has_source from Config
2023-05-09 22:22:27 -07:00
Hansung Kim
54a3e3cf72
Initiate memtrace DPI only when trace_read_ready
...
This is required because otherwise we might overwrite into
the Verilog registers that contain a valid trace line that
was missed by downstream when it was not ready. Basically
whenever trace_read_cycle stalls, we also want to stall
__in_* registers.
2023-05-08 14:34:52 -07:00
Hansung Kim
6b97b77572
Revert SimMemTrace.v to use posedge clock
...
Doing function calls inside @(*) causes lint errors. Instead, remove
staging registers to eliminate 1 cycle latency between DPI call and
when output is visible to Chisel.
2023-05-08 00:14:48 -07:00
Hansung Kim
ba600db7e4
Backport SimMemTrace fix
2023-05-07 23:54:49 -07:00
