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6866b537d6fcf50bae9c96f33a4bcba28da283e2
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Author SHA1 Message Date
Hansung Kim
6866b537d6 Separate out InflightCoalReqTable into a module 2023-03-10 15:28:28 -08:00
Hansung Kim
da58ab552f Construct entry for in-flight coalesced requests table 2023-03-10 14:22:43 -08:00
Hansung Kim
93b198e0f6 Properly assert ready/valid for all TL channels 2023-03-10 00:22:38 -08:00
Hansung Kim
e523b4235a Make placeholder for inflight coalesced request table 2023-03-09 23:48:12 -08:00
Hansung Kim
13552593c8 Check legal from Get and Put 2023-03-09 22:56:34 -08:00
Hansung Kim
46d3109e82 Skip instantiating queue for the edge from master node 2023-03-09 22:39:49 -08:00
Hansung Kim
9bfb813e1b Thread -> Lane 
"thread" is confusing, unify to lane when denoting a hardware SIMD lane
inside a single warp.
 2023-03-09 22:09:21 -08:00
Hansung Kim
a495149869 Connect coal master node to identitynode internally 
Instead of exposing master node to downstream, wrap everything inside
the IdentityNode with N+1:N+1 edges. The inward edges exposed to the
upstream nodes are only N edges. Needs more testing.
 2023-03-09 20:53:52 -08:00
Hansung Kim
f0069ba3ad Set lgSize=0 as memtrace addresses are not aligned 
This is TODO, we need to have a logic inside MemTraceDriver that aligns
these addresses to word boundaries and sets the right masks, similar to
how an actual core issues load/stores.
 2023-03-09 20:50:34 -08:00
Hansung Kim
babbdf9550 Left out fromSource 2023-03-08 18:36:47 -08:00
Hansung Kim
70b715645c Parameterize sourceId width for reg entry 2023-03-08 18:32:06 -08:00
Hansung Kim
a2ceb8c628 Fix sourceId collision by using a counter 2023-03-08 18:31:03 -08:00
Vamber Yang
f623cc89a7 Merged with origin/graphics, MemTracer able to read and write according to tracefile 2023-03-08 17:38:59 -08:00
Vamber Yang
0de09daa05 MemTracer able to read and write according to trace file, also support thread_id skipping in trace file 2023-03-08 17:34:10 -08:00
Hansung Kim
39db60f42b Queue -> ShiftQueue, preserve source id of incoming reqs 2023-03-08 16:49:36 -08:00
Hansung Kim
41ecf6bc20 Squelch debug prints in SimMemTrace 2023-03-07 17:53:09 -08:00
Hansung Kim
1bc8cbb925 Instantiate FIFOs to buffer TL reqs per each lane 2023-03-07 15:10:00 -08:00
Hansung Kim
337272764b Test with Get() and doc source ID allocation 2023-03-06 23:15:30 -08:00
Hansung Kim
760d3f5aa2 Add example where IdentityNode.out has different data from .in 2023-03-06 21:56:56 -08:00
Hansung Kim
c7651e26f4 Organize Diplomacy node structure of CoalescingUnit 
IdentityNode with numThreads edges + master TL node with additional 1
edge for the new coalesced requests.
 2023-03-06 16:17:52 -08:00
Hansung Kim
aa2d52a197 Merge Coalescing{Logic, Entry} to CoalescingUnit 
CoalescingUnit acts as the top module that abstracts TL wrangling away
from outside.
 2023-03-05 17:33:37 -08:00
Hansung Kim
6fea4be050 Refactor with zip 2023-03-05 16:59:06 -08:00
Hansung Kim
db9be56191 Properly connect each lane to TL node 2023-03-05 00:18:29 -08:00
Hansung Kim
ef1608505f Use single SimMemTrace instance 2023-03-04 23:55:20 -08:00
Hansung Kim
172ab51355 Fix formatting and unused warnings 2023-03-03 23:44:50 -08:00
Hansung Kim
5f55a7578f Recover lost changes 2023-03-03 22:36:54 -08:00
Hansung Kim
dcb49f7683 Doc update 2023-03-03 21:22:56 -08:00
Vamber Yang
1a322f5ca7 Merge remote-tracking branch 'origin/graphics' into HEAD 
Pulling remote changes before pushing
 2023-03-03 20:40:41 -08:00
Vamber Yang
c3129b8c5c Tracer supports N threads, communicates with Coalescing with TL + Diplomacy interface 2023-03-03 20:27:29 -08:00
Hansung Kim
97fec01620 Receive per-lane valid from SimMemTrace 2023-03-03 18:09:58 -08:00
Hansung Kim
c1e8f4ef86 Maintain cycle inside Verilog instead of C 
The Verilog wrapper maintains the cycle state, and C parser becomes a
combinational logic which Verilog queries to check if there is a request
in the trace at a specific {cycle, core_id, thread_id}.
 2023-03-03 16:38:32 -08:00
Hansung Kim
664959f723 Parameterize SimMemTrace Verilog module to number of threads 2023-03-03 16:16:07 -08:00
Hansung Kim
44cf6fbb2f Update SimMemTrace csrc from submodule 2023-03-03 16:14:11 -08:00
Hansung Kim
b57c0e2b7d SimMemTrace: parse batch instead of at every cycle 2023-03-02 17:24:36 -08:00
Hansung Kim
24f4ee93ac Add TL client node to MemTraceDriver 2023-02-27 23:35:14 -08:00
Hansung Kim
a06b5faa3c Wrap memtrace DPI module with a Chisel driver module 2023-02-27 19:55:22 -08:00
Hansung Kim
9025729c0e Emit address in addition to cycle 2023-02-27 17:36:54 -08:00
Hansung Kim
0ebaed5f1b Communicate trace cycle data from C++ to Chisel 2023-02-27 14:40:49 -08:00
Hansung Kim
72de4bca66 Initial parsing of memory trace file in C++ 2023-02-27 13:47:30 -08:00
Hansung Kim
80e4b5c734 Set up simple DPI for trace-driven testing 2023-02-26 20:39:19 -08:00
Hansung Kim
5bf8bb8217 Add empty unit test for coalescing unit 
copied over from WithTLXbarUnitTests
 2023-02-22 16:42:18 -08:00
Huy Vo
1b733e7cf0 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-03-13 12:34:39 -07:00
Andrew Waterman
2607153b67 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-03-09 02:08:55 -08:00
Yunsup Lee
4f00bcc760 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-02-29 17:12:02 -08:00
Huy Vo
0fd777f480 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-02-26 17:24:23 -08:00
Andrew Waterman
71c8d3fd41 reorganize directory structure 2012-02-08 15:13:08 -08:00