Inside DPI code, have a vector of unique_ptrs that act as handles to multiple
different trace logger instances. Each logger instance is instantiated in a
single instance of the Verilog module, and multiple of these Verilog modules may
be instantiated in the Chisel module (see simReq and simResp in MemTraceLogger).
TODO: since TileLink rounds all address down to a multiple of its beat
size (8 in the current code), we can't directly compare the memory trace
input to its output. Need to take masks into account.
