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Create separate Configs for synthesizable dummy testbenches

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This commit is contained in:
Hansung Kim
2023-05-08 17:51:24 -07:00
parent f6be54a122
commit fd0d09691b
1 changed files with 9 additions and 6 deletions
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15
src/main/scala/tilelink/Coalescing.scala
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@@ -14,7 +14,7 @@ import freechips.rocketchip.unittest._
// TODO: find better place for these // TODO: find better place for these
case class SIMTCoreParams(nLanes: Int = 4, tracefilename: String = "undefined") case class SIMTCoreParams(nLanes: Int = 4, tracefilename: String = "undefined")
case object SIMTCoreKey extends Field[Option[SIMTCoreParams]](None) case object SIMTCoreKey extends Field[Option[SIMTCoreParams]](None /*default*/)
trait InFlightTableSizeEnum extends ChiselEnum { trait InFlightTableSizeEnum extends ChiselEnum {
val INVALID: Type val INVALID: Type
@@ -1609,18 +1609,22 @@ class DummyDriverImp(outer: DummyDriver, config: CoalescerConfig)
// A dummy harness around the coalescer for use in VLSI flow. // A dummy harness around the coalescer for use in VLSI flow.
// Should not instantiate any memtrace modules. // Should not instantiate any memtrace modules.
class DummyCoalescer(implicit p: Parameters) extends LazyModule { class DummyCoalescer(implicit p: Parameters) extends LazyModule {
val driver = LazyModule(new DummyDriver(defaultConfig)) val numLanes = p(SIMTCoreKey).get.nLanes
val rams = Seq.fill(defaultConfig.numLanes + 1)( // +1 for coalesced edge println(s"============ numLanes: ${numLanes}")
val config = defaultConfig.copy(numLanes = numLanes)
val driver = LazyModule(new DummyDriver(config))
val rams = Seq.fill(config.numLanes + 1)( // +1 for coalesced edge
LazyModule( LazyModule(
// NOTE: beatBytes here sets the data bitwidth of the upstream TileLink // NOTE: beatBytes here sets the data bitwidth of the upstream TileLink
// edges globally, by way of Diplomacy communicating the TL slave // edges globally, by way of Diplomacy communicating the TL slave
// parameters to the upstream nodes. // parameters to the upstream nodes.
new TLRAM(address = AddressSet(0x0000, 0xffffff), new TLRAM(address = AddressSet(0x0000, 0xffffff),
beatBytes = (1 << defaultConfig.dataBusWidth)) beatBytes = (1 << config.dataBusWidth))
) )
) )
val coal = LazyModule(new CoalescingUnit(defaultConfig)) val coal = LazyModule(new CoalescingUnit(config))
coal.cpuNode :=* driver.node coal.cpuNode :=* driver.node
rams.foreach(_.node := coal.aggregateNode) rams.foreach(_.node := coal.aggregateNode)
@@ -1641,7 +1645,6 @@ class DummyCoalescerTest(timeout: Int = 500000)(implicit p: Parameters)
// tracedriver --> coalescer --> tracelogger --> tlram // tracedriver --> coalescer --> tracelogger --> tlram
class TLRAMCoalescerLogger(filename: String)(implicit p: Parameters) extends LazyModule { class TLRAMCoalescerLogger(filename: String)(implicit p: Parameters) extends LazyModule {
val numLanes = p(SIMTCoreKey).get.nLanes val numLanes = p(SIMTCoreKey).get.nLanes
println(s"============ numLanes: ${numLanes}")
val config = defaultConfig.copy(numLanes = numLanes) val config = defaultConfig.copy(numLanes = numLanes)
val driver = LazyModule(new MemTraceDriver(config, filename)) val driver = LazyModule(new MemTraceDriver(config, filename))