From fd0d09691b1fd0865d646ac72dce33eb186bb3f8 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Mon, 8 May 2023 17:51:24 -0700 Subject: [PATCH] Create separate Configs for synthesizable dummy testbenches --- src/main/scala/tilelink/Coalescing.scala | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/src/main/scala/tilelink/Coalescing.scala b/src/main/scala/tilelink/Coalescing.scala index 2ce2e6d..5bef07d 100644 --- a/src/main/scala/tilelink/Coalescing.scala +++ b/src/main/scala/tilelink/Coalescing.scala @@ -14,7 +14,7 @@ import freechips.rocketchip.unittest._ // TODO: find better place for these case class SIMTCoreParams(nLanes: Int = 4, tracefilename: String = "undefined") -case object SIMTCoreKey extends Field[Option[SIMTCoreParams]](None) +case object SIMTCoreKey extends Field[Option[SIMTCoreParams]](None /*default*/) trait InFlightTableSizeEnum extends ChiselEnum { val INVALID: Type @@ -1609,18 +1609,22 @@ class DummyDriverImp(outer: DummyDriver, config: CoalescerConfig) // A dummy harness around the coalescer for use in VLSI flow. // Should not instantiate any memtrace modules. class DummyCoalescer(implicit p: Parameters) extends LazyModule { - val driver = LazyModule(new DummyDriver(defaultConfig)) - val rams = Seq.fill(defaultConfig.numLanes + 1)( // +1 for coalesced edge + val numLanes = p(SIMTCoreKey).get.nLanes + println(s"============ numLanes: ${numLanes}") + val config = defaultConfig.copy(numLanes = numLanes) + + val driver = LazyModule(new DummyDriver(config)) + val rams = Seq.fill(config.numLanes + 1)( // +1 for coalesced edge LazyModule( // NOTE: beatBytes here sets the data bitwidth of the upstream TileLink // edges globally, by way of Diplomacy communicating the TL slave // parameters to the upstream nodes. new TLRAM(address = AddressSet(0x0000, 0xffffff), - beatBytes = (1 << defaultConfig.dataBusWidth)) + beatBytes = (1 << config.dataBusWidth)) ) ) - val coal = LazyModule(new CoalescingUnit(defaultConfig)) + val coal = LazyModule(new CoalescingUnit(config)) coal.cpuNode :=* driver.node rams.foreach(_.node := coal.aggregateNode) @@ -1641,7 +1645,6 @@ class DummyCoalescerTest(timeout: Int = 500000)(implicit p: Parameters) // tracedriver --> coalescer --> tracelogger --> tlram class TLRAMCoalescerLogger(filename: String)(implicit p: Parameters) extends LazyModule { val numLanes = p(SIMTCoreKey).get.nLanes - println(s"============ numLanes: ${numLanes}") val config = defaultConfig.copy(numLanes = numLanes) val driver = LazyModule(new MemTraceDriver(config, filename))