From f6be54a12265ae893314410f6bd2691aba31a30e Mon Sep 17 00:00:00 2001
From: Hansung Kim <hansung_kim@berkeley.edu>
Date: Mon, 8 May 2023 17:32:31 -0700
Subject: [PATCH] Set up proper Config system for numLanes

TODO: tracefilename should not really be inside SIMTCoreParam.
---
 src/main/scala/tilelink/Coalescing.scala      | 18 +++++---
 src/main/scala/tilelink/TracerSystemMem.scala | 45 ++++++-------------
 2 files changed, 25 insertions(+), 38 deletions(-)

diff --git a/src/main/scala/tilelink/Coalescing.scala b/src/main/scala/tilelink/Coalescing.scala
index 8ded755..2ce2e6d 100644
--- a/src/main/scala/tilelink/Coalescing.scala
+++ b/src/main/scala/tilelink/Coalescing.scala
@@ -5,12 +5,17 @@ package freechips.rocketchip.tilelink
 import chisel3._
 import chisel3.util._
 import chisel3.experimental.ChiselEnum
-import org.chipsalliance.cde.config.Parameters
+import org.chipsalliance.cde.config.{Parameters, Field}
 import freechips.rocketchip.diplomacy._
 // import freechips.rocketchip.devices.tilelink.TLTestRAM
 import freechips.rocketchip.util.MultiPortQueue
 import freechips.rocketchip.unittest._
 
+// TODO: find better place for these
+case class SIMTCoreParams(nLanes: Int = 4, tracefilename: String = "undefined")
+
+case object SIMTCoreKey extends Field[Option[SIMTCoreParams]](None)
+
 trait InFlightTableSizeEnum extends ChiselEnum {
   val INVALID: Type
   val FOUR: Type
@@ -1635,14 +1640,15 @@ class DummyCoalescerTest(timeout: Int = 500000)(implicit p: Parameters)
 
 // tracedriver --> coalescer --> tracelogger --> tlram
 class TLRAMCoalescerLogger(filename: String)(implicit p: Parameters) extends LazyModule {
-  // TODO: use parameters for numLanes
-  val numLanes = defaultConfig.numLanes
+  val numLanes = p(SIMTCoreKey).get.nLanes
+  println(s"============ numLanes: ${numLanes}")
+  val config = defaultConfig.copy(numLanes = numLanes)
 
-  val driver = LazyModule(new MemTraceDriver(defaultConfig, filename))
+  val driver = LazyModule(new MemTraceDriver(config, filename))
   val coreSideLogger = LazyModule(
     new MemTraceLogger(numLanes, filename, loggerName = "coreside")
   )
-  val coal = LazyModule(new CoalescingUnit(defaultConfig))
+  val coal = LazyModule(new CoalescingUnit(config))
   val memSideLogger = LazyModule(new MemTraceLogger(numLanes + 1, filename, loggerName = "memside"))
   val rams = Seq.fill(numLanes + 1)( // +1 for coalesced edge
     LazyModule(
@@ -1650,7 +1656,7 @@ class TLRAMCoalescerLogger(filename: String)(implicit p: Parameters) extends Laz
       // edges globally, by way of Diplomacy communicating the TL slave
       // parameters to the upstream nodes.
       new TLRAM(address = AddressSet(0x0000, 0xffffff),
-        beatBytes = (1 << defaultConfig.dataBusWidth))
+        beatBytes = (1 << config.dataBusWidth))
     )
   )
 
diff --git a/src/main/scala/tilelink/TracerSystemMem.scala b/src/main/scala/tilelink/TracerSystemMem.scala
index e0d495b..ca31864 100644
--- a/src/main/scala/tilelink/TracerSystemMem.scala
+++ b/src/main/scala/tilelink/TracerSystemMem.scala
@@ -1,44 +1,25 @@
-
 package freechips.rocketchip.tilelink
 
-import chisel3._
-import chisel3.util._
 import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes}
-import org.chipsalliance.cde.config.{Parameters, Field, Config}
+import freechips.rocketchip.subsystem.{BaseSubsystem}
+import org.chipsalliance.cde.config.{Parameters, Config}
 
-// class class, consumed by WithGPUTacer config and GPUTracerKey
-
-case class GPUTracerConfig(numLanes: Int, traceFile : String) // FIXME, add lane number and file name
-
-case object GPUTracerKey extends Field[Option[GPUTracerConfig]](None)
-
-
-
-// Both LazyModule of Tracer and Impl are both in Coalescing.scala
-
-
-//The trait is attached to DigitalTop of Chipyard system, informing it indeed has the ability 
-//to attach GPU tracer node  onto the system bus
+// The trait is attached to DigitalTop of Chipyard system, informing it indeed
+// has the ability to attach GPU tracer node onto the system bus
 trait CanHaveGPUTracer { this: BaseSubsystem =>
   implicit val p: Parameters
 
-  //p(GPUTracerKey) is the mechnimism to pass Config's parameter down to lazymodule
-  p(GPUTracerKey) .map { k =>
-    val config = p(GPUTracerKey).get
-    val tracer = LazyModule(new MemTraceDriver(defaultConfig, config.traceFile)(p))
-    // Must use :=* to ensure the N edges from Tracer doesn't get merged into 1 when connecting to SBus
+  p(SIMTCoreKey).map { _ =>
+    val config = p(SIMTCoreKey).get
+    val tracer = LazyModule(new MemTraceDriver(defaultConfig, config.tracefilename)(p))
+    // Must use :=* to ensure the N edges from Tracer doesn't get merged into 1
+    // when connecting to SBus
     sbus.fromPort(Some("gpu-tracer"))() :=* tracer.node
   }
 }
 
-
 //This is used by Chip Level Config, the config which creates the SoC
-class WithGPUTracer(numLanes: Int, traceFile : String) extends Config((site, here, up) => {
-    case GPUTracerKey => Some( GPUTracerConfig(numLanes, traceFile) )
-}
-)
-
-
-
-
+class WithGPUTracer(numLanes: Int, tracefilename: String)
+    extends Config((_, _, _) => { case SIMTCoreKey =>
+      Some(SIMTCoreParams(numLanes, tracefilename))
+    })